CMOS-Photonic Integration via Template-Assisted Bonding
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Solution Overview
Problem
The integration of advanced electronic functions with compound semiconductor devices on silicon substrates is hindered by the incompatibility of processing techniques and the high cost of using III-V materials, limiting the fabrication of monolithically integrated optoelectronic circuits.
Innovation Solution
Template-assisted bonding of semiconductor wafers allows for the integration of silicon-germanium CMOS devices with compound semiconductor photonic devices on a silicon-on-insulator substrate, enabling wafer-scale processing and reducing the need for expensive III-V materials by using them sparingly where required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compound semiconductor substrates are used for photonic devices, then optical performance is improved, but fabrication cost increases significantly
Solution Approach 1:
The invention divides the integration process into separate stages: photonic devices are fabricated on compound semiconductor substrates, diced into individual dies, then mounted on an assembly substrate. This segmentation allows optimization of each component independently while controlling overall cost through selective use of expensive materials only where optically required.
Solution Approach 2:
Compound semiconductor materials are used locally only in regions where optical performance is critical (photonic devices), while silicon-based CMOS devices are used for electronic functions. This local quality approach minimizes the use of expensive III-V materials while maintaining optimal performance in critical areas.
2Ease of manufacture
If silicon substrates are used for integrated circuits, then manufacturing cost is reduced, but light emission and optical amplification capabilities are lost
Solution Approach 1:
The invention merges silicon-based CMOS devices with compound semiconductor photonic devices through template-assisted bonding. This combination allows the system to leverage the cost advantages and electronic performance of silicon while incorporating the optical emission and amplification capabilities of compound semiconductors.
Solution Approach 2:
The invention creates a composite integrated circuit structure combining silicon and compound semiconductor materials. Each material is used in its optimal application domain: silicon for electronic processing and compound semiconductors for optical functions, achieving both cost-effectiveness and functional versatility.
3Manufacturing precision
If template-assisted bonding is used for wafer-scale processing, then alignment precision is improved, but process complexity increases
Solution Approach 1:
Alignment templates are prepared in advance with precise positioning features before the bonding process. This preliminary action establishes accurate alignment references that guide the subsequent wafer bonding, achieving high precision without requiring complex real-time alignment systems.
Solution Approach 2:
Alignment templates serve as intermediary elements between the photonic device wafers and the assembly substrate. These templates mediate the alignment process by providing stable, pre-fabricated reference structures that simplify the bonding operation while ensuring precise positioning.
Data Source
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Figure 3A~3E
AI summary
A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.