CMOS Pixel Array Defect Tolerance via High Impedance Buffer

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Solution Overview

Problem

Conventional CMOS image sensor pixel arrays are vulnerable to defects such as erroneous connections between row select lines and supply or column output lines, leading to permanent selection of entire rows and rendering the array non-operational, which hampers the fabrication of large area image sensors.

Innovation Solution

The implementation of a buffer amplifier that can be selectively put into a high impedance state by controlling its input, either through a disable line or by setting the supply line to ground, allowing defective rows to be disabled and preventing voltage output, thereby enabling the use of defect-free rows while concealing defects using interpolation techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional CMOS pixel arrays are used with standard row select lines, then the array can be manufactured using standard processes, but a single defect in a row select line can cause entire rows to be permanently selected, rendering the entire array non-operational

Engineering Contradiction:
Improvearray operabilityVSAvoidsensitivity to row select line defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The row selection function is segmented across two independent select lines (first row select line and second row select line) instead of using a single select line. Each select line controls a separate transistor (first select transistor and second select transistor) in series between the buffer amplifier output and the column output line. This segmentation ensures that a defect in one select line does not cause permanent selection of the entire row, as both select lines must be active for the row to be selected, thereby improving array operability while reducing sensitivity to row select line defects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pixel array is designed with redundant select lines and transistors before defects can occur. The dual select line architecture provides a built-in protective mechanism that prevents catastrophic failure from single-point defects. By anticipating potential defects in row select lines during the design phase, the system ensures continuous operation even when defects are present, effectively cushioning against harmful effects before they can render the array non-operational.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If two select transistors and two row select lines are used to protect against single defects, then the array becomes more resistant to single row select line defects, but the array remains vulnerable to double short errors and the complexity increases

Engineering Contradiction:
Improveresistance to single defectsVSAvoidnumber of select transistors and control lines
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first and second row select lines serve dual purposes: they individually control their respective select transistors for normal row selection operation, and collectively provide defect protection by requiring both to be functional for any row to be selected. This multi-functionality allows the same select lines to serve both operational and protective roles, reducing the need for additional dedicated protective circuitry and thereby limiting the increase in device complexity while maintaining resistance to single defects.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If additional transistors and control lines are added to protect against defects, then defect tolerance improves, but the manufacturing precision requirements and fabrication difficulty increase

Engineering Contradiction:
Improvedefect toleranceVSAvoidfabrication process constraints
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention changes the selection parameter from a single control line to multiple control lines (two row select lines instead of one). This parameter change increases defect tolerance because a single defect no longer determines the operational status of entire rows. The additional transistors and control lines are integrated into the standard CMOS fabrication process, maintaining compatibility with existing manufacturing precision requirements while improving reliability through architectural redundancy rather than requiring tighter fabrication tolerances.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2076018B1Pixel array with reduced sensitivity to defects
Publication Date: 2014.10.08 CMOSIS
  • EP2076018B1 patent drawingFigure 1~3
  • EP2076018B1 patent drawingFigure 4~5
  • EP2076018B1 patent drawingFigure 6~7

AI summary

An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element. The array is configured such that, in the event of a defect in a row select line, the first supply line is set to ground, or a low voltage, and the reset switch is turned on to put the buffer amplifier into the high impedance state.