CMOS Pixel Layout With Deep Ground Doping for Lower Cross-Talk
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS image sensors face challenges in improving electrical characteristics, such as integration density and reducing cross-talk between pixel regions, due to limitations in pixel isolation and dopant region design, which affect signal-to-noise ratio and reliability.
Innovation Solution
The design includes a substrate with pixel isolation patterns and ground dopant regions, where the bottom surface of the ground dopant region is positioned lower than the floating diffusion region, and a connection pattern in a trench that connects ground dopant regions, reducing the area occupied by the ground dopant and enhancing the size of active patterns, thereby improving electrical characteristics and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ground dopant region is positioned at a higher level (conventional design), then the manufacturing process is simpler, but the integration density is reduced and cross-talk between pixel regions increases
Solution Approach 1:
The patent applies dimensionality change by positioning the ground dopant region at a lower level beneath the floating diffusion region, utilizing the vertical dimension to improve electrical characteristics and reduce cross-talk between pixel regions while maintaining manufacturing feasibility
2Reliability
If the ground dopant region occupies larger area (conventional design), then the electrical stability is improved, but the area available for active patterns is reduced
Solution Approach 1:
The patent resolves this contradiction by moving the ground dopant region to a lower vertical level, allowing it to provide electrical stability without occupying horizontal space that would be needed for active patterns, thus increasing the active pattern area while maintaining electrical reliability
3Reliability
If more interconnection lines are used (conventional design), then the electrical connections are more robust, but the device complexity and parasitic capacitances increase
Solution Approach 1:
The patent extracts and eliminates unnecessary interconnection lines by repositioning the ground dopant region to a lower level, which provides more direct electrical paths and reduces parasitic capacitances, thereby maintaining robust electrical connections with fewer interconnection elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration density and reliability of the image sensor by reducing electrical failures and noise, while increasing the size of active patterns and reducing the number of interconnection lines, thus improving overall electrical performance.
Implementation Method 1
The photodiode may convert incident light into an electrical signal
Data Source
AI summary
An image sensor includes a substrate including first and second pixel regions adjacent to each other, the substrate including first and second surfaces opposite to each other, a pixel isolation pattern in the substrate to define the first and second pixel regions, a transfer gate on the first surface of the substrate of the first pixel region, a floating diffusion region adjacent to a side of the transfer gate, a first ground dopant region adjacent to the first surface of the substrate in the first pixel region, and a second ground dopant region adjacent to the first surface of the substrate in the second pixel region. A bottom surface of the first ground dopant region is located at a lower level than a bottom surface of the floating diffusion region.