CMOS Pixel Layout With Shared Isolation for Lower Flicker Noise

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Solution Overview

Problem

Complementary metal-oxide semiconductor (CMOS) image sensors face poor noise performance due to the size reduction of pixel devices to accommodate full-depth deep trench isolation structures, which increases flicker noise and decreases the accuracy and reliability of images.

Innovation Solution

The image sensor design includes a readout transistor that extends over the isolation structure between adjacent pixel sensors, functioning as two transistors in parallel, reducing effective channel resistance and parasitic capacitance, and increasing the effective length of the conductive channel under the gate electrode to decrease noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pixel device size is reduced to accommodate full-depth deep trench isolation structures, then isolation effectiveness is improved, but flicker noise increases and image accuracy deteriorates

Engineering Contradiction:

Improveisolation effectivenessVSAvoidimage accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The pixel device is divided into multiple smaller pixel units arranged in an array, with each unit having its own deep trench isolation structure. This segmentation allows each pixel unit to maintain adequate isolation effectiveness while reducing the overall device footprint, thereby preventing flicker noise increase that would occur with excessive size reduction of a single large pixel device.

Inventive Principle:

Principle #1Segmentation

2Productivity

If pixel device size is reduced to accommodate full-depth deep trench isolation structures, then device density is improved, but noise performance deteriorates

Engineering Contradiction:

Improvedevice densityVSAvoidflicker noise

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

Adjacent pixel devices share common deep trench isolation structures at their boundaries. This merging approach increases device density by eliminating redundant isolation structures between pixels, while each pixel maintains sufficient isolation to prevent flicker noise generation. The shared isolation structures achieve high-density packing without sacrificing noise performance.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If pixel device size is reduced, then manufacturing cost is decreased, but noise performance and reliability deteriorate

Engineering Contradiction:

Improvemanufacturing costVSAvoidnoise performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The pixel devices are arranged in a two-dimensional array with deep trench isolation structures extending vertically through multiple layers. This dimensional approach allows compact lateral spacing (reducing manufacturing cost) while maintaining adequate vertical isolation depth (preserving noise performance). The multi-layer isolation structure achieves cost-effective miniaturization without compromising reliability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240170508A1Pixel device layout to reduce pixel noise

Publication Date: 2024.05.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip include a first photodetector in a semiconductor substrate. A first gate electrode overlies the semiconductor substrate and comprises a first sidewall over the first photodetector. A first source/drain region and a second source/drain region are in the semiconductor substrate and adjacent to the first sidewall. A first isolation element is in the semiconductor substrate and adjacent to the first sidewall. The first isolation element is spaced between the first and second source/drain regions.