CMOS Pixel Vertical Charge Transfer Layout for Linear Extraction
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in maintaining linear charge extraction paths, leading to decreased charge transfer efficiency due to design restrictions.
Innovation Solution
The proposed imaging apparatus features a two-dimensional lattice pattern of pixels with a photoelectric conversion unit, a gate electrode, and a diffusion region arrayed along the substrate thickness direction, along with an embedded insulating film to prevent electron avalanches, enhancing charge transfer efficiency and reducing image quality degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical gate electrode is inserted into silicon to form a deep region for charge accumulation, then the charge accumulation capacity is improved, but the charge transfer efficiency deteriorates due to non-linear extraction path
Solution Approach 1:
The patent transitions from a planar charge transfer path to a three-dimensional vertical path by inserting the gate electrode into the silicon substrate to form a deep accumulation region. This dimensional change allows simultaneous achievement of deep charge storage and efficient linear extraction through the vertically-aligned photoelectric conversion unit, gate electrode, and diffusion region configuration.
Solution Approach 2:
The gate electrode is nested within the silicon substrate, forming a deep accumulation region that contains the charge. The photoelectric conversion unit, gate electrode, and diffusion region are vertically nested along the substrate thickness direction, creating a compact structure that maintains linear charge extraction path while achieving deep charge accumulation.
2Force
If multiple vertical gate electrodes are used to increase modulation force, then the charge modulation capability is improved, but the device complexity increases
Solution Approach 1:
The gate electrode structure is segmented into multiple vertical gates inserted at different positions within the silicon substrate. Each vertical gate electrode provides independent modulation capability, and their combined effect increases the total modulation force while maintaining a relatively simple overall structure through the vertical configuration.
Solution Approach 2:
The patent employs a composite structure combining multiple vertical gate electrodes with the silicon substrate and insulating films. This composite approach enhances the modulation force through the combined electric fields of multiple gates while managing complexity through systematic integration of different materials and structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves charge transfer efficiency and suppresses image quality issues like white spots by ensuring linear charge extraction and reducing electric field concentration.
Implementation Method 1
a photoelectric conversion unit that photoelectrically converts incident light
Implementation Method 2
a gate electrode that transfers charge accumulated in the photoelectric conversion unit; an electric field is applied to perform reading
Data Source
AI summary
A decrease in charge transfer efficiency is suppressed. An imaging apparatus according to an embodiment includes a plurality of pixels arrayed in a two-dimensional lattice pattern, in which each of the pixels includes a photoelectric conversion unit (PD) that photoelectrically converts incident light, a gate electrode that transfers charge accumulated in the photoelectric conversion unit, and a diffusion region (FD) to which the charge transferred from the photoelectric conversion unit flows, and the photoelectric conversion unit, the gate electrode, and the diffusion region are arrayed in a semiconductor substrate along a substrate thickness direction of the semiconductor substrate.