CMOS Image Sensor Pixels with Hybrid Bonded Stacked Substrates
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Solution Overview
Problem
Conventional image sensors with global shutter scanning mode require additional charge storage nodes, increasing pixel area and cost, especially for high dynamic range (HDR) operations, which complicates the design and increases expenses.
Innovation Solution
The implementation of a double reset circuit or active reset circuit on multiple substrates within the image sensor, allowing for efficient charge transfer and storage without generating kTC-reset noise, enabling HDR global shutter operation without the need for additional pixel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional charge storage nodes are added to enable global shutter scanning mode, then global shutter functionality is achieved, but pixel area increases and manufacturing cost increases
Solution Approach 1:
The patent utilizes the third dimension (vertical depth) by implementing multiple substrates stacked together. Charge storage nodes are distributed across different substrates at different depths, allowing global shutter functionality without increasing the two-dimensional pixel area. The microlens array focuses light onto photodiodes on the first substrate, while charge storage regions are positioned on subsequent substrates, effectively using vertical space to resolve the area contradiction.
Solution Approach 2:
The patent employs a nested structure where multiple functional layers are stacked vertically. The first substrate contains photodiodes that generate charge, the second substrate contains charge storage regions that store the charge, and additional substrates may contain further storage or processing elements. This nesting allows multiple functions (light sensing, charge generation, charge storage) to coexist within a compact vertical footprint, avoiding pixel area expansion.
2Adaptability or versatility
If additional charge storage nodes are added for high dynamic range global shutter pixels, then high dynamic range capability is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent achieves high dynamic range by utilizing vertical stacking of multiple substrates with different charge storage capacities. The first charge storage node and second charge storage node are positioned on different substrates at different depths, allowing simultaneous storage of multiple charge levels without increasing lateral pixel area. This dimensional approach enables HDR functionality while maintaining manufacturing efficiency through standardized stacked fabrication processes.
3Quantity of substance
If conventional charge storage methods are used, then charge storage is achieved, but kTC-reset noise is generated
Solution Approach 1:
The patent segments the charge storage function into multiple distinct charge storage nodes positioned on different substrates. Instead of using a single large storage node that would generate significant kTC-reset noise, the total charge storage capacity is divided among multiple smaller nodes (first charge storage node on second substrate, second charge storage node on third substrate). This segmentation reduces the noise generated by each individual reset operation while maintaining the total charge storage capacity needed for high dynamic range imaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high dynamic range global shutter imaging with reduced noise and cost, maintaining large aperture efficiency and resolution while minimizing kTC-reset noise, thus optimizing pixel design for electronic devices.
Implementation Method 1
a photodiode formed in the first substrate
Data Source
AI summary
A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.