Self-Biased CMOS PLL Clock Generator for Low Jitter Tuning
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Solution Overview
Problem
Conventional clock generators with self-biased phase locked loops face challenges in achieving low frequency and phase jitter across a wide output clock frequency range, particularly due to varying oscillator stage currents and VCO gains, which affect noise power and overall clock jitter.
Innovation Solution
The integrated CMOS clock generator employs a dual bias generator and voltage controlled oscillator block configuration, where each oscillator block operates within a partial frequency range, with selective switching and individual loop filter components to reduce VCO gain and increase current, thereby minimizing clock jitter. This configuration includes two oscillator blocks with separate bias generators and loop filter capacitors, allowing for independent tuning and reduced noise influence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single voltage controlled oscillator is used to cover a wide frequency range, then the frequency tuning range is extended, but the clock jitter increases due to varying oscillator stage currents and VCO gains
Solution Approach 1:
The patent divides the frequency tuning range into multiple partial ranges, each covered by a separate voltage controlled oscillator. The first VCO covers a first partial frequency range with optimized current and VCO gain characteristics, while the second VCO covers a second partial frequency range. This segmentation allows each oscillator to be optimized for its specific range, minimizing jitter within each segment while collectively providing wide frequency coverage.
2Reliability
If oscillator stage current is increased to reduce noise power, then clock jitter is reduced, but power consumption increases
Solution Approach 1:
The patent assigns different oscillator stage currents to different VCOs based on their respective frequency ranges and jitter requirements. The first VCO operates with a first oscillator stage current optimized for its partial frequency range, while the second VCO operates with a second oscillator stage current optimized for its range. This local optimization reduces overall power consumption compared to running a single high-current VCO across the entire frequency range.
3Reliability
If VCO gain is reduced to minimize noise influence, then clock jitter is reduced, but frequency tuning range is limited
Solution Approach 1:
The patent segments the frequency tuning range into multiple partial ranges, each covered by a dedicated VCO with optimized VCO gain. The first VCO has a first VCO gain optimized for minimal noise influence in its frequency range, while the second VCO has a second VCO gain optimized for its range. This allows each VCO to operate with low gain (reducing jitter) while the combination provides wide overall frequency coverage.
4Reliability
If a dual bias generator configuration is used to reduce jitter, then frequency and phase jitter are reduced, but device complexity increases
Solution Approach 1:
The patent implements a dual bias generator configuration where the first bias generator provides bias currents optimized for the first VCO and operating conditions, while the second bias generator provides bias currents optimized for the second VCO and its operating conditions. This segmented biasing approach reduces frequency and phase jitter by ensuring each VCO operates with optimally tuned bias conditions, while the modular structure keeps complexity manageable.
Data Source
AI summary
An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.