CMOS Fractional-N PLL Synthesizer With Isolated Power Routing
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Solution Overview
Problem
Existing location receivers face challenges with high power consumption and large chip area due to the implementation of phase locked loop (PLL) synthesizers, particularly in CMOS logic, which limits their efficiency and portability, especially in hand-held GPS applications.
Innovation Solution
Implementing a PLL synthesizer using standard CMOS logic with a fractional-N divider, integer divider, and phase frequency detector, which eliminates the need for dc bias current and reduces power consumption and chip area, scalable with process technology, while overcoming supply and ground noise issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If PLL synthesizer is implemented in standard CMOS logic, then power consumption and chip area are reduced, but supply and ground noise issues arise
Solution Approach 1:
The patent introduces an intermediary mechanism by using separate power and ground networks specifically for the PLL synthesizer block, isolated from the rest of the circuit through dedicated routing paths. This intermediary structure allows the PLL to operate in CMOS logic with reduced power consumption while preventing its noise from affecting other circuits and isolating it from external noise sources.
Solution Approach 2:
The patent segments the power distribution network by creating distinct power and ground domains. The PLL synthesizer is assigned its own dedicated power supply pins and ground connections, separated from other functional blocks. This segmentation isolates the noise-generating PLL circuitry from sensitive analog and digital sections, allowing CMOS implementation without noise propagation issues.
2Area of stationary object
If PLL synthesizer components are integrated in standard CMOS, then chip area is reduced, but noise from rail-to-rail transitions increases
Solution Approach 1:
The patent applies local quality by creating specialized power and ground routing exclusively for the PLL synthesizer block, different from the general power distribution network. This localized approach allows the PLL to benefit from CMOS integration area savings while its unique noise characteristics are managed through dedicated routing paths that prevent noise coupling to other sensitive circuits.
Solution Approach 2:
Dedicated power and ground routes act as intermediaries between the noisy PLL synthesizer and the rest of the system. These intermediary pathways provide controlled impedance and isolation, allowing the PLL to operate in compact CMOS implementation while preventing noise from reaching sensitive analog front-ends or digital logic sections.
3Use of energy by moving object
If dc bias current is eliminated from PLL synthesizer, then power consumption is reduced, but circuit operation reliability may be affected
Solution Approach 1:
The patent changes the operational parameters of the PLL synthesizer by eliminating dc bias current requirements through careful selection of circuit topologies and operating points. By modifying biasing schemes and using dynamic power management techniques, the circuit maintains reliable operation while achieving significant power consumption reduction, enabling portable GPS receiver applications.
Data Source
AI summary
A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block.