CMOS Device Non-Straight PN-Boundary Layout
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Solution Overview
Problem
CMOS devices face challenges in minimizing well proximity effects without increasing device size, especially when adjacent MOSFET pairs have different dimensions, and in efficiently using die area while operating at various operating points.
Innovation Solution
The implementation of a PN-boundary as a chain of line segments, with alternating straight and non-straight segments, allows for denser transistor packing and improved delay balancing by specifying the boundary in a way that satisfies geometrical constraints and optimizes substrate use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the PN-boundary is positioned to reduce well proximity effects by maintaining optimal distance from transistors, then well proximity effects are reduced, but the device area increases
Solution Approach 1:
The PN-boundary is segmented into multiple line segments rather than being a single straight line. This segmentation allows the boundary to deviate from a straight path and optimally position itself relative to transistors of different sizes, reducing well proximity effects without requiring additional device area
Solution Approach 2:
The PN-boundary incorporates curved or non-linear segments that allow it to adapt to the varying dimensions of adjacent transistors. This curvature enables the boundary to maintain optimal distances from transistors of different sizes along its path, effectively reducing well proximity effects while fitting within the same device area
2Loss of time
If adjacent MOSFET pairs are dimensioned differently to balance delays, then delay balancing is improved, but the layout complexity increases
Solution Approach 1:
The PN-boundary is designed with locally varying properties through its segmented structure, where different segments have different orientations and positions tailored to the specific requirements of adjacent transistor pairs. This allows each local region to be optimized for its specific transistor dimensions and delay requirements
Solution Approach 2:
The boundary parameters (position, orientation, curvature) are varied along its length to match the varying transistor dimensions. This parameter variation allows the layout to accommodate differently sized MOSFET pairs while maintaining systematic design rules and manageable complexity
Data Source
AI summary
A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells.For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.