CMOS Power Amplifier Efficiency via Distributed Active Transformer
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Solution Overview
Problem
Conventional CMOS power amplifiers face challenges in achieving high efficiency and small size due to low substrate resistivity, metal ohmic loss, heat generation, and breakdown voltage issues, particularly in RF systems, where integration is difficult and parasitic signals affect performance.
Innovation Solution
The design incorporates a CMOS power amplifier with a distributed active transformer structure, utilizing a primary winding on one layer and secondary windings on an upper layer for improved coupling, reducing current crowding and parasitic capacitance, and increasing the K factor to enhance efficiency and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are concentrated on one spot to achieve integration, then device complexity is reduced, but heat generation increases and reliability degrades
Solution Approach 1:
The patent segments the transistor layout by distributing them across different locations on the chip rather than concentrating them in one spot. This spatial segmentation reduces local heat generation while maintaining integration, directly addressing the contradiction between device complexity reduction and heat management.
2Loss of energy
If LC resonant impedance transformation network is used for power amplifier, then power amplifier efficiency is improved, but device size increases due to external components
Solution Approach 1:
The patent merges the LC resonant impedance transformation network with the power amplifier circuit itself, integrating the impedance transformation function into the amplifier structure. This eliminates the need for separate external inductors and capacitors, thereby maintaining high power amplifier efficiency while reducing overall device size.
Solution Approach 2:
The patent designs the power amplifier circuit to serve multiple functions simultaneously - amplification and impedance transformation. By making the amplifier circuit universal for both purposes, external dedicated impedance transformation components are eliminated, reducing device size while maintaining efficiency.
3Ease of manufacture
If CMOS technique is used for RF system integration, then manufacturing cost is reduced and integration is achieved, but noise characteristics and parasitic signals deteriorate performance above 1 GHz
Solution Approach 1:
The patent converts the inherently noisy CMOS substrate into a beneficial element by using it as an integrated inductor. The substrate noise and parasitic effects are transformed from harmful factors into useful magnetic coupling mechanisms, enabling impedance transformation while maintaining low cost and high integration. This directly addresses the contradiction between manufacturing ease and noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the output transformer efficiency, power amplifier efficiency, and maximum output power, while reducing size and heat generation, thereby overcoming the limitations of conventional CMOS power amplifiers.
Implementation Method 1
a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding
Data Source
AI summary
A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.