CMOS Output Buffer Pre-Driver for Slew Rate and Crowbar Control
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Solution Overview
Problem
CMOS output buffers face issues with large current transients causing power/ground bouncing noise and crowbar current due to the large sizes of PMOS and NMOS transistors, which existing solutions either fail to address simultaneously or require complex and area-inefficient designs.
Innovation Solution
The implementation of a pre-driver circuit with a pull-up PMOS transistor and a pull-down NMOS transistor, coupled with Schmitt trigger circuits and logic gate networks that control the slew rate and crowbar current by adjusting threshold voltages and switching thresholds to prevent simultaneous turn-on of both transistors, thereby minimizing voltage spikes and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large sizes in PMOS and NMOS transistors are used to achieve high driving strengths, then the driving capability is improved, but large current transient and crowbar current are generated causing power/ground bouncing noise
Solution Approach 1:
The patent segments the single large transistor switching operation into multiple smaller transistor switching operations by dividing the output buffer into parallel transistor groups (first group, second group, third group) that switch sequentially. This segmentation reduces the instantaneous current transient while maintaining the overall driving capability through the combined effect of all groups.
Solution Approach 2:
The patent applies preliminary action by using delay elements to pre-coordinate the switching timing of transistor groups. The delay elements ensure that transistors in different groups switch at staggered times, with the first group switching before the second group, and the second group before the third group, thereby preventing simultaneous switching that would cause crowbar current.
2Manufacturing precision
If conventional RC network with large resistor values is used for slew rate control, then the slew rate control is improved, but the circuit complexity and area increase
Solution Approach 1:
The patent replaces the conventional RC network (analog timing circuit) with a digital delay element-based timing control system. The delay elements use digital logic circuits to generate delayed control signals, substituting the analog resistor-capacitor timing mechanism with a digital sequential timing mechanism, thereby reducing area and simplifying the circuit while maintaining slew rate control functionality.
Solution Approach 2:
The patent introduces delay elements as intermediary components between the control logic and the transistor gates. These delay elements act as mediators that sequence the activation of different transistor groups, providing precise timing control without requiring large RC networks. The delay elements translate control signals into sequentially delayed gate control signals.
3Speed
If both PMOS and NMOS transistors are turned on simultaneously for fast switching, then the switching speed is improved, but large crowbar current flows from VDD to VSS
Solution Approach 1:
The patent applies periodic action by implementing a sequential switching pattern where different transistor groups are activated in a specific sequence rather than simultaneously. The first group of transistors switches first, followed by the second group after a delay, and then the third group, creating a periodic/staggered activation pattern that prevents simultaneous conduction while maintaining fast overall switching performance.
Solution Approach 2:
The patent uses preliminary action through delay elements that pre-coordinate the switching sequence. Before enabling the full output buffer, the control circuit activates the first transistor group preliminarily, then after a predetermined delay enables the second and third groups, ensuring that transistors are turned on in a controlled sequence that avoids crowbar current while achieving fast switching.
Data Source
AI summary
An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down NMOS transistor.