CMOS Prober Chip for Parallel Semiconductor Characterization
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Solution Overview
Problem
Current prober systems for semiconductor device and thin film material testing are complex, expensive, and inefficient, particularly at the nanoscale, where precise navigation and alignment of multiple probe tips are challenging, leading to potential damage and limited ability to perform parallel characterization of multiple devices or circuits.
Innovation Solution
The development of CMOS prober chips with multiple probe tips, interlayer metals, and dielectrics, where the probe tips are conductively connected and can be freely suspended or spring-loaded, allowing for parallel characterization of multiple devices or circuits by aligning and contacting them simultaneously, reducing measurement cycle times and mitigating tip collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple independent scanning probe microscopes are coupled to enable imaging and electrical characterization, then the ability to perform parallel characterization is improved, but the device complexity and cost increase prohibitively
Solution Approach 1:
The patent merges multiple probe tips, sensing components, actuation components, and electronics onto a single integrated prober chip platform. This consolidation enables parallel characterization of multiple devices while avoiding the prohibitive complexity and cost of coupling multiple independent scanning probe microscopes.
Solution Approach 2:
The prober chip is designed as a universal platform that can perform both imaging and electrical characterization functions simultaneously through its integrated multiple probe tips and supporting components, eliminating the need for separate specialized systems.
2Productivity
If multiple probe tips are positioned within nanometers of each other to characterize multiple devices, then the productivity is improved, but the risk of tip collisions and damage increases
Solution Approach 1:
The probe tips are pre-positioned on the prober chip at predetermined locations with appropriate spacing before the measurement process begins. This preliminary arrangement ensures that tips remain separated during operation, enabling fast parallel measurement while preventing collisions.
3Measurement precision
If precision probes are used to make contact with transistors for electrical characterization, then the measurement precision is improved, but the ease of operation deteriorates due to navigation difficulty at the nanoscale
Solution Approach 1:
The system segments the navigation task by using a single nano-positioner to move the entire prober chip platform rather than individually controlling multiple complex probe tip assemblies. This simplifies operation while maintaining precision through the integrated design.
Data Source
AI summary
Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.