CMOS Process Corner Detection Circuit Using Transistor Comparators
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Solution Overview
Problem
Designers of digital and analog circuits face challenges in optimizing performance across various process corners for CMOS devices due to uncertainties in transistor parameters such as effective gate length, threshold voltage, and gate oxide thickness, leading to differences in 'strength' between NMOS and PMOS transistors.
Innovation Solution
A circuit and method for determining process corners in CMOS devices, comprising a CMOS monitoring circuit with NMOS and PMOS transistors, reference circuits for generating reference voltages, and comparators to evaluate transistor voltages against reference values, allowing for accurate characterization of transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variations are present in CMOS transistors, then transistor parameters such as effective gate length, threshold voltage, and gate oxide thickness vary, but this leads to uncertainty in transistor strength and performance across different process corners
Solution Approach 1:
The patent applies parameter changes by systematically varying process conditions during manufacturing to create distinct process corners (FF, SS, FS, SF). Each corner represents a specific combination of transistor parameters (effective gate length, threshold voltage, gate oxide thickness) that defines a unique performance characteristic. This allows the circuit to adapt to and characterize different parameter sets rather than relying on a single nominal value.
2Productivity
If circuit designers optimize for typical CMOS pair characteristics, then the circuit performs well at TT process corner, but performance degrades at extreme process corners (FF, SS, FS, SF)
Solution Approach 1:
The patent implements dynamics by making the circuit configuration adaptable through switching mechanisms. The circuit can dynamically reconfigure its operation mode based on the detected process corner, transitioning between different operational states to optimize performance for each specific corner condition rather than being fixed at a single optimization point.
Solution Approach 2:
The patent changes operational parameters (such as bias voltages, current levels, or switching thresholds) based on the identified process corner. By detecting which corner the circuit is operating at and adjusting parameters accordingly, the circuit maintains optimal performance across FF, SS, FS, and SF conditions rather than being limited to TT corner optimization.
3Ease of manufacture
If a fixed circuit configuration is used, then the circuit is simple to manufacture, but it cannot adapt to different process corners and environmental conditions
Solution Approach 1:
The patent applies self-service by enabling the circuit to automatically characterize its own process corner without requiring external testing equipment or complex measurement setups. The circuit uses its existing functional blocks to generate test signals, measure performance characteristics, identify the process corner, and store this information for later use, all autonomously within the device itself.
Solution Approach 2:
The patent implements universality by designing the circuit to perform multiple functions using the same hardware resources. The functional blocks serve both normal operational purposes and process corner characterization purposes, eliminating the need for separate dedicated test circuits and maintaining manufacturing simplicity while adding adaptability.
Data Source
AI summary
A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising an NMOS transistor and a PMOS transistor of the integrated circuit; reference circuit comprising elements for generating a reference voltage for an NMOS transistor and a reference voltage for a PMOS transistor; a first comparator for comparing a voltage generated by the NMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a NMOS transistor; and a second comparator for comparing a voltage generated by the PMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a PMOS transistor. A method for determining a process corner for CMOS devices of an integrated circuit is also disclosed.