CMOS PUF Circuit Using Subthreshold Leakage for Runtime Querying
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Solution Overview
Problem
Current SRAM and DRAM based PUF generators face limitations such as restricted access during boot time and lack of strong PUF configuration, necessitating a solution that allows runtime querying with a robust PUF configuration.
Innovation Solution
A decay-based CMOS pseudo-DRAM PUF generator is introduced, comprising a plurality of PUF cells with CMOS transistors, which generate a PUF signature by monitoring transient discharge behaviors and comparing voltage values to trigger points, enabling runtime querying and strong PUF configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF generator is used, then PUF configuration is provided, but access is restricted to boot time only
Solution Approach 1:
The patent transitions from using SRAM cell initial states (binary configuration) to measuring subthreshold leakage current characteristics (analog parameter). This parameter change enables runtime querying while maintaining PUF configuration strength, as subthreshold current varies continuously with transistor threshold voltage and can be measured at any operational time.
Solution Approach 2:
The patent replaces the mechanical/memory-based SRAM cell state reading with an electrical measurement of subthreshold leakage current. This substitution allows the PUF to be queried during runtime through electrical current measurement rather than being restricted to boot-time memory state capture.
2Adaptability or versatility
If DRAM-based PUF generator is used, then runtime querying is enabled, but strong PUF configuration is not provided
Solution Approach 1:
The patent uses subthreshold leakage current measurement which directly reflects transistor threshold voltage variations. This parameter provides strong PUF configuration because threshold voltage is fundamentally determined by manufacturing process variations, while enabling runtime querying through continuous current measurement capability.
Solution Approach 2:
The patent employs standard CMOS transistors that naturally exhibit subthreshold leakage current, a typically unwanted effect. By converting this short-living, normally discarded characteristic into a useful PUF measurement signal, the patent achieves both runtime querying and strong configuration without requiring specialized long-lived components.
3Reliability
If inherent process variations are used for PUF generation, then unique PUF signatures are achieved, but manufacturing precision is reduced
Solution Approach 1:
The patent converts manufacturing process variations, which are typically considered defects reducing product quality, into the fundamental source of PUF uniqueness. By measuring subthreshold leakage current that directly reflects these variations, the patent transforms manufacturing imprecision into a reliable security feature.
Solution Approach 2:
The patent shifts focus from measuring parameters that require high manufacturing precision (such as SRAM cell initial states) to measuring subthreshold leakage current, which naturally amplifies and reflects transistor threshold voltage variations. This parameter change makes manufacturing variations beneficial rather than harmful.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution allows for efficient runtime querying and provides a strong PUF configuration, overcoming the limitations of existing SRAM and DRAM based PUF generators by leveraging inherent process variations for unique and reliable PUF signatures.
Implementation Method 1
Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current
Implementation Method 2
variations in transistor threshold voltage and subthreshold leakage current caused by inherent variations in a semiconductor manufacturing process
Data Source
AI summary
Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.