CMOS Read Transistor Leakage Reduction via Dynamic Voltage Control
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Solution Overview
Problem
The energy efficiency of memory cells in portable devices is limited by significant leakage current during non-read operations, which reduces battery life due to increased power consumption.
Innovation Solution
A CMOS read transistor is used with the read word line and bit line maintained at a common voltage during non-read operations to prevent or reduce leakage current, and temporarily changed to a particular voltage level during read operations until data is sensed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory array geometry is reduced to increase storage capacity, then the storage density is improved, but the leakage current increases leading to higher power consumption
Solution Approach 1:
The patent changes the voltage parameter of the read word line dynamically: during non-read operations, the read word line voltage is raised to match the read bit line voltage (both at Vdd), which turns off the CMOS read transistor and eliminates leakage current. During read operations, the read word line voltage is lowered to enable the transistor to conduct. This parameter change resolves the contradiction by making leakage current dependent on operational state rather than geometry scaling.
2Ease of operation
If the memory cell uses a CMOS read transistor with read word line and read bit line at different voltages during non-read operations, then the transistor can be easily activated for reading, but significant leakage current flows through the transistor during idle periods
Solution Approach 1:
The patent makes the voltage relationship between read word line and read bit line dynamic rather than static. During non-read operations, both lines are at the same voltage (Vdd), turning off the transistor and eliminating leakage. During read operations, the read word line voltage is temporarily reduced while the read bit line remains at Vdd, enabling the transistor to activate. This dynamic voltage adjustment resolves the contradiction between ease of activation and leakage reduction.
Solution Approach 2:
The patent applies periodic voltage adjustment to the read word line: it maintains high voltage (Vdd) during non-read periods to prevent leakage, then periodically lowers the voltage during read operations to enable transistor activation. This periodic action pattern resolves the contradiction by ensuring the transistor is only active when needed, eliminating continuous leakage while maintaining readiness for read operations.
3Speed
If the read word line is maintained at a low voltage level during non-read operations to enable quick read activation, then the read operation speed is improved, but the leakage current through the CMOS read transistor increases
Solution Approach 1:
The patent prepares the read word line voltage in advance based on the operational state: before read operations begin, the voltage is lowered to enable quick transistor activation, while during non-read operations, the voltage is maintained at Vdd to prevent leakage. This preliminary voltage preparation resolves the contradiction by ensuring the transistor can activate quickly when needed without maintaining low voltage continuously, thus avoiding continuous leakage.
Data Source
AI summary
A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.