CMOS Image Sensor Read Transistor Noise Reduction
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Solution Overview
Problem
CMOS image sensors face significant noise issues, particularly in low light conditions, due to sources like read noise and 1/f noise, which are not adequately addressed by existing technologies.
Innovation Solution
The design incorporates a CMOS image sensor with specific transistor configurations, including a read transistor with reduced gate length and width, and a pinched diode structure, to minimize noise. The read transistor has a gate oxide thickness less than other transistors, and its body region is isolated from the body regions of transfer and reset transistors, with biased voltages to maximize measurement range while preventing voltage exceedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional MOS transistors with uniform gate dimensions are used in all pixel circuits, then manufacturing is simplified, but read noise and 1/f noise increase significantly
Solution Approach 1:
The patent applies local quality by giving the readout transistor (source follower) different gate dimensions (smaller gate length and/or width) compared to transfer and reset transistors. This localized differentiation reduces read noise and 1/f noise in the readout path without affecting other circuit functions, directly improving measurement precision while maintaining manageable manufacturing complexity through a controlled single parameter variation.
2Measurement precision
If the gate oxide thickness is reduced to minimize noise, then read noise decreases, but the maximum voltage that can be applied between transistor terminals is limited
Solution Approach 1:
The patent changes the gate oxide thickness parameter specifically for the readout transistor to a thinner value than used in transfer and reset transistors. This parameter change reduces read noise and 1/f noise while the patent manages the voltage constraint by ensuring the readout transistor operates within its reduced voltage tolerance through appropriate circuit design and biasing.
3Measurement precision
If photogenerated charges are transferred to a capacitive readout node, then light intensity measurement is enabled, but various noise sources affect the measurement accuracy
Solution Approach 1:
The patent applies local quality by optimizing the readout transistor specifically for noise reduction with thinner gate oxide and smaller gate dimensions, while keeping transfer and reset transistors with standard dimensions. This targeted optimization reduces read noise and 1/f noise in the measurement path, directly improving illumination level measurement precision without compromising other pixel functions.
Solution Approach 2:
The patent changes physical parameters (gate oxide thickness and gate dimensions) of the readout transistor to reduce noise sources affecting the measurement. The thinner gate oxide reduces read noise and 1/f noise, while the smaller gate area reduces capacitance and associated noise, thereby improving measurement accuracy despite the increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces 1/f component noise and leakage noise, enhancing the sensor's performance in low light conditions by minimizing read noise and maintaining dynamic range.
Implementation Method 1
Each pixel contains a photodiode used in inverse mode, whose junction capacitance is discharged by a photocurrent according to the received light intensity
Implementation Method 2
a first MOS transistor connecting a second terminal of the photodiode to a pixel readout node; a second MOS transistor connecting the readout node to a node of application of a second reference potential
Data Source
Figure 1~4
AI summary
The invention relates to a CMOS pixel comprising: a photodiode (101) having one terminal connected to a GND potential and another terminal connected to a read node (SN) by a first MOS transistor (103); a second MOS transistor (105) connecting the read node (SN) to a VDDH potential; and a third MOS transistor (307) whose gate (407) is connected to the read node (SN), the transistors (103, 105, 307) having the same gate insulator thickness, in which the third transistor (307) has a gate length and/or width less than those of the first (103) and second (105) transistors, in that the VDDH-GND difference is greater than the nominal voltage of the third MOS transistor (307), and in that the body or drain region of the third transistor (307) is connected to a VL potential between the VDDH and GND potentials.