Capacitive-Coupled CMOS Reference Voltage Circuit for Fast Start-Up
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Solution Overview
Problem
Existing reference voltage generating circuits face challenges in achieving low power consumption while maintaining high power supply rejection ratio, fast start-up time, and stability across varying temperatures and processes, leading to increased chip area and complexity.
Innovation Solution
A self-biased and capacitive-coupled reference voltage generating circuit with a stacked diode-connected architecture, utilizing a cascode current mirror circuit and capacitive coupling to reduce power consumption and chip area, and eliminate the need for bipolar junction transistors, thereby improving temperature stability and suppressing power interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low power consumption design is implemented (less than 100 nW), then power consumption is reduced, but start-up time increases to tens of milliseconds or more
Solution Approach 1:
The patent employs a startup circuit that pre-charges capacitive nodes before normal operation begins. This preliminary action ensures that critical nodes have sufficient voltage headroom to quickly establish the reference voltage output, reducing start-up time from tens of milliseconds to acceptable levels while maintaining the low power consumption regime of less than 100 nW during steady-state operation
2Use of energy by moving object
If low power consumption design is implemented (less than 100 nW), then power consumption is reduced, but power supply rejection ratio bandwidth is limited
Solution Approach 1:
The patent introduces an intermediate capacitive coupling stage that acts as a buffer between the low-power reference voltage generation core and the external circuitry. These capacitors serve as energy storage intermediaries that maintain voltage stability and extend the PSRR bandwidth by filtering power supply noise without requiring additional active power consumption, thus resolving the contradiction between low power operation and wide PSRR bandwidth
3Use of energy by moving object
If low power consumption operation is implemented, then power consumption is reduced, but impedance between power supply and output increases, slowing voltage switching
Solution Approach 1:
The startup circuit performs preliminary charging of the capacitive nodes in the reference voltage generation path before normal operation begins. This pre-charging action reduces the initial impedance bottleneck, enabling faster voltage switching and response when the circuit transitions from off to on state, while maintaining low power consumption during steady-state operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced power consumption, shortened start-up time, and extended bandwidth, while maintaining stability across a wide temperature range, effectively addressing the limitations of existing designs by enhancing the power supply rejection ratio and reducing chip area.
Implementation Method 1
a first capacitive coupling circuit and a second capacitive coupling circuit. The first capacitive coupling circuit includes a first capacitor C1 and a second capacitor C2, two terminals of the first capacitor C1 are coupled between the gate of the fifth N-type transistor MN5 and the serial connection node of the fifth N-type transistor MN5 and the sixth P-type transistor MP6, a terminal of the second capacitor C2 is coupled to the serial connection node of the fifth N-type transistor MN5 and the sixth P-type transistor MP6, and another terminal of the second capacitor C2 is coupled between the first output circuit and the first stacked diode-connected circuit
Data Source
AI summary
A low-power CMOS reference voltage generating with enhanced power supply rejection ratio (PSRR) and fast start-up time is disclosed. The reference voltage generating is generated by the stacked diode-connected MOS transistors (SDMT) architecture to reduce the dependence on process, voltage and temperature. The self-biased and capacitor coupled architecture can shorten the start-up time without increasing power consumption and improve the bandwidth of the power supply rejection ratio. This design is implemented using a CMOS process, which can achieve stabilization time of 0.2 ms. Under the same power consumption, this design is 274 times better than a design without a start-up time enhancement. The power supply rejection ratio measured at 100 Hz is −73.5 dB. In the temperature range of −40 to 130° C., the average temperature coefficient is 62 ppm/° C.