CMOS Reset Circuit With Impedance Buffer for Fast Supply Changes
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Solution Overview
Problem
Conventional reset signal generating circuits for CMOS logical circuits malfunction when power supply voltage changes rapidly, due to the threshold voltage of the inverter changing in response to the power supply voltage, leading to unstable output levels.
Innovation Solution
A reset device with a power supply voltage monitoring unit using a comparator to compare the detected voltage with a reference voltage, and a reset signal outputting unit incorporating CMOS inverters with impedance units between the MOS transistors and the power supply or ground lines, allowing adjustment of the switching voltage to maintain stable output levels even during rapid power supply changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional CMOS inverter is used to generate reset signal, then the circuit structure is simple, but the inverter malfunctions when power supply voltage changes rapidly
Solution Approach 1:
The patent introduces an impedance unit as an intermediary element between the power supply voltage line/ground line and the CMOS inverter. This impedance unit (resistor or capacitor) acts as a buffer that filters out rapid voltage changes before they reach the inverter, preventing the inverter from malfunctioning while maintaining the overall simplicity of the circuit structure.
Solution Approach 2:
The impedance unit is placed in advance before the voltage change reaches the inverter, providing cushioning protection. The capacitor specifically stores energy and smooths out rapid voltage transitions, preventing the inverter from experiencing harmful voltage fluctuations that would cause malfunction.
2Adaptability or versatility
If the threshold voltage of the inverter changes with power supply voltage, then the inverter adapts to voltage changes, but the output levels become unstable during rapid voltage transitions
Solution Approach 1:
The impedance unit serves as a mediator that decouples the direct relationship between power supply voltage changes and inverter input voltage changes. By filtering the voltage transitions, it allows the inverter to adapt to gradual voltage changes while protecting it from rapid transitions that would cause output instability.
Solution Approach 2:
The impedance unit changes the temporal characteristics of the voltage parameter reaching the inverter. It transforms rapid voltage changes into slower, controlled transitions, allowing the inverter to maintain stable output levels while still adapting to the overall voltage level changes.
3Device complexity
If no impedance unit is added, then the circuit remains simple, but the reset signal output is influenced by rapid power supply voltage changes
Solution Approach 1:
The impedance unit is introduced as a minimal additional component that acts as a buffer between the power supply and the reset signal generation circuitry. This simple addition effectively filters out noise and rapid voltage changes without significantly increasing circuit complexity.
Solution Approach 2:
The impedance unit provides beforehand protection by filtering voltage fluctuations before they reach the reset signal generation circuit. The capacitor stores energy during voltage peaks and releases it during voltage dips, cushioning the circuit against rapid changes and ensuring stable reset signal output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a stable reset signal output without being influenced by rapid changes in the power supply voltage, maintaining the output levels consistent and preventing malfunctions in CMOS inverters.
Implementation Method 1
the impedance unit may be a resistance element having a resistance value within a range from not less than 100 kΩ to not more than 3 MΩ
Data Source
AI summary
A disclosed reset device for outputting a reset signal based on a magnitude of an input power supply voltage includes: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the unit outputting the reset signal. An impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line.