CMOS Image Sensor Reset Shield Line
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Solution Overview
Problem
Conventional CMOS image sensors face limitations in image lag due to shallow potential wells at floating diffusion nodes, especially as pixel size decreases, leading to reduced signal sensitivity and conversion gain.
Innovation Solution
The introduction of a reset shield line that reduces reset capacitance by extending across the coupling portion between the reset transistor and the floating diffusion node, effectively increasing the impact of floating node capacitance and maintaining a deeper potential well, thereby reducing image lag.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to achieve higher resolution, then image sensor resolution is improved, but potential well depth at floating diffusion node decreases leading to increased image lag
Solution Approach 1:
A shield line is introduced as an intermediary conductive structure between the reset transistor and the floating diffusion node. This shield line acts as a mediator to control and reduce the reset capacitance coupling, thereby mitigating the charge injection effect that causes image lag in miniaturized pixels without affecting the pixel size reduction for higher resolution
2Reliability
If reset capacitance is reduced to decrease image lag, then image quality is improved, but charge injection control becomes more difficult
Solution Approach 1:
The invention changes the capacitance parameter by introducing a shield line with specific conductive properties and geometric configuration. By adjusting the shield line's position, size, and connection points, the reset capacitance can be precisely controlled to optimize image quality while maintaining manageable charge injection characteristics
3Reliability
If floating node capacitance impact is increased to maintain deeper potential well, then image lag is reduced, but reset capacitance must be minimized
Solution Approach 1:
The shield line is strategically positioned locally near the floating diffusion node to enhance the impact of floating node capacitance in the critical region where charge accumulation occurs. This localized approach deepens the potential well where needed without requiring global changes to the entire pixel structure, thereby managing capacitance balancing more effectively
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the voltage potential at the floating diffusion node, reducing image lag and improving signal readout, particularly at high signal levels, by limiting charge injection from the reset transistor.
Implementation Method 1
The introduction of a reset shield line that reduces reset capacitance by extending across the coupling portion between the reset transistor and the floating diffusion node
Data Source
AI summary
Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node.