CMOS Image Sensor Reset Shield Line for Image Lag Reduction
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Solution Overview
Problem
Conventional CMOS image sensors face limitations in image lag due to shallow potential wells at floating diffusion nodes, especially as pixel size decreases, leading to reduced signal sensitivity and conversion gain.
Innovation Solution
The introduction of a reset shield line that reduces reset capacitance by extending across the coupling portion between the reset transistor and the floating diffusion node, effectively deepening the potential well and minimizing charge injection, thereby enhancing image lag performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to achieve higher resolution, then image sensor resolution is improved, but potential well depth at floating diffusion node deteriorates leading to increased image lag
Solution Approach 1:
A shield line is introduced as an intermediary conductive structure between the reset transistor and the floating diffusion node. This shield line acts as a mediator to reduce the parasitic capacitance (reset capacitance) between these two components, thereby deepening the potential well at the floating diffusion node and reducing image lag in miniaturized pixels
2Object-affected harmful factors
If reset capacitance between reset transistor and floating diffusion node is reduced, then potential well depth is improved, but device complexity increases due to additional shield line structure
Solution Approach 1:
The shield line is designed to serve multiple functions: it reduces reset capacitance between the reset transistor and floating diffusion node, provides electrostatic shielding to minimize charge injection effects, and can be integrated with existing pixel circuit layouts without requiring fundamentally new device structures. This multi-functionality justifies the additional structural element
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reset shield line reduces image lag at high signal levels by maintaining a deeper potential well at the floating diffusion node, improving signal sensitivity and conversion gain in CMOS image sensors.
Implementation Method 1
The introduction of a reset shield line that reduces reset capacitance by extending across the coupling portion between the reset transistor and the floating diffusion node
Implementation Method 2
photodiode 101 and floating diffusion node 106 are reset during a reset phase... After the reset phase, the integration phase is commenced by de-asserting transfer signal TX and reset signal RST and permitting incident light to charge photodiode 101. The voltage or charge on photodiode 101 is indicative of the intensity of light incident of photodiode 101 during the integration phase
Data Source
AI summary
Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node.