CMOS MOSFET-Stacked RF Power Amplifier With Double Push-Pull Linearity
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Solution Overview
Problem
RF power amplifiers face challenges in achieving high power efficiency, linearity, integration, and output power while maintaining low manufacturing costs, due to limitations in transistor design, nonlinear characteristics, and the need for additional components and protection circuits.
Innovation Solution
The implementation of a main amplification circuit using stacks of PMOS and NMOS transistors in a double push-pull architecture, with RC filter structures and shared bias DC current, allows for efficient voltage distribution and nonlinear compensation without additional components, eliminating the need for VSWR protection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors M3 and M4 are stacked on top of core transistors M1 and M2 to share voltage drop, then transistor safety is ensured, but die area increases and power efficiency is limited
Solution Approach 1:
The voltage sharing function is segmented from the core transistors M1 and M2 and assigned to dedicated voltage-sharing transistors M3 and M4. This segmentation allows the core transistors to operate at optimal low voltage while the voltage-sharing transistors handle the high voltage portion, ensuring transistor safety without requiring the core transistors to be oversized for voltage withstand capability.
Solution Approach 2:
The voltage-sharing transistors M3 and M4 serve multiple functions: they protect the core transistors from overvoltage, enable high output power operation, and contribute to the overall amplification function. This multi-functionality reduces the need for separate protection circuits and minimizes die area.
2Reliability
If transistors M5 and M6 are added to compensate for nonlinearity, then linearity is improved, but capacitive load increases and power efficiency decreases
Solution Approach 1:
The nonlinearity compensation function is merged into the existing voltage-sharing transistors M3 and M4 rather than adding separate compensation transistors. The push-pull configuration of M3 and M4 inherently provides nonlinearity compensation while maintaining low capacitive load, thus improving linearity without sacrificing power efficiency.
3Power
If supply voltage Vdd is increased to obtain large output power, then output power is improved, but transistor breakdown risk increases
Solution Approach 1:
The high supply voltage Vdd is segmented across multiple transistor stacks. The core transistors M1 and M2 operate at low voltage (less than 1.2V in 22 nm CMOS process), while the voltage-sharing transistors M3 and M4 handle the remaining voltage drop. This segmentation enables the amplifier to achieve high output power (about 1W) without exposing any single transistor to breakdown-prone high voltage.
4Reliability
If additional protection circuits are added to protect against output impedance mismatch, then transistor protection is improved, but manufacturing cost increases
Solution Approach 1:
The voltage-sharing transistors M3 and M4 automatically protect the core transistors against output impedance mismatch conditions without requiring external protection circuits. When output mismatch occurs, the voltage-sharing transistors inherently limit the voltage stress on core transistors through their voltage-sharing mechanism, providing self-protection functionality that reduces manufacturing cost.
Data Source
AI summary
An amplification circuit for RF power amplifiers is provided. The circuit includes two PMOS amplification modules and two NMOS amplification modules; each module includes a CSCG structure composed of a stack of K transistors. The first PMOS module and the first NMOS module are connected in series between a supply voltage and ground; gates of main amplification transistors of the first PMOS module and the first NMOS module are connected to a non-inverting input, and outputs of the first PMOS module and the first NMOS module are connected together to form an inverting output. The second PMOS module and the second NMOS module are similarly connected. Both the first and the second modules will be connected side-by-side as a pseudo differential structure to provide double push-pull function to the load. The present disclosure simultaneously achieves high power efficiency, and high linearity.