CMOS RF Circuits With Segmented PMOS And Deep N-Well Isolation
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Solution Overview
Problem
RF CMOS circuits face challenges in achieving high performance, low noise, and immunity to noise interference, particularly due to the trade-off between NMOS and PMOS components, where PMOS devices with buried channels offer lower flicker noise but struggle with threshold voltage reduction, and surface channel PMOS devices increase flicker noise, while digital logic circuits disturb adjacent analogue circuits with noise.
Innovation Solution
A CMOS process integrating both surface channel and buried channel PMOS components, with selectively doped polysilicon gates, and deep n-well junction isolation to separate noise-sensitive analogue and digital circuits, allowing for low noise and low voltage operation without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If PMOS devices use buried channel structure, then flicker noise is reduced, but threshold voltage cannot be lowered sufficiently
Solution Approach 1:
The patent segments the PMOS device structure into two types: buried channel PMOS for low-noise applications and surface channel PMOS for low-voltage applications. This segmentation allows each device type to be optimized for its specific function without compromise.
Solution Approach 2:
The patent applies local quality by using different channel structures in different regions of the chip. Buried channel PMOS devices are used in regions where low noise is critical (e.g., RF front-end), while surface channel PMOS devices are used in regions where low voltage operation is needed (e.g., digital logic).
2Adaptability or versatility
If PMOS devices use surface channel structure, then threshold voltage can be lowered, but flicker noise increases significantly
Solution Approach 1:
The patent segments the PMOS device structure into two types: buried channel PMOS for low-noise applications and surface channel PMOS for low-voltage applications. This segmentation allows each device type to be optimized for its specific function without compromise.
Solution Approach 2:
The patent applies local quality by using different channel structures in different regions of the chip. Buried channel PMOS devices are used in regions where low noise is critical (e.g., RF front-end), while surface channel PMOS devices are used in regions where low voltage operation is needed (e.g., digital logic).
3Productivity
If digital logic circuits are placed near analogue circuits, then integration density increases, but noise interference from digital circuits disturbs analogue circuits
Solution Approach 1:
The patent extracts noise-sensitive analogue circuits from the general CMOS substrate by forming them in a separate well structure (e.g., n-well or p-well isolation). This physical extraction creates electrical isolation that prevents digital noise from coupling into analogue circuits while maintaining high integration density.
Solution Approach 2:
The patent uses well structures and isolation regions as intermediary elements between digital and analogue circuits. These intermediaries provide electrical isolation and noise filtering, allowing digital and analogue circuits to coexist on the same chip without significant noise interference.
Data Source
AI summary
A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.