CMOS Ring VCO Impedance Compensation for Low Supply Sensitivity
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Solution Overview
Problem
High-speed voltage-controlled oscillators (VCOs) in CMOS ICs are sensitive to perturbations in supply voltage, leading to increased jitter and bit error rates in communication systems, particularly due to noise coupling from the power supply, which existing techniques struggle to mitigate effectively without consuming extra power or requiring additional regulator circuitry.
Innovation Solution
A CMOS ring oscillator design incorporating a CML negative impedance compensation circuit with cross-coupled transistors and resistive biasing, along with a CML interpolating delay cell, counteracts impedance changes due to supply variations, reducing frequency variation and periodic jitter without the need for a dedicated clean power supply or extra regulator circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated clean power supply or extra regulator circuitry is used to reduce supply sensitivity, then the VCO's power supply rejection ratio improves, but the power consumption increases and device complexity increases
Solution Approach 1:
The VCO circuit uses its own internal current sources and transistors to generate compensating signals that counteract supply noise effects. The differential pair and current mirrors within the VCO itself are configured to create opposing impedance changes that cancel out the harmful supply variations, eliminating the need for external regulator circuitry and reducing power consumption.
Solution Approach 2:
The patent introduces an intermediary compensation mechanism using differential transistor pairs and current mirrors that act as mediators between the supply voltage and the VCO core. These intermediate circuit elements sense supply variations and generate compensating signals that counteract the noise before it reaches the frequency-determining elements, improving PSRR without requiring dedicated clean power supplies.
2Reliability
If a dedicated clean power supply or extra regulator circuitry is used to reduce supply sensitivity, then the VCO's power supply rejection ratio improves, but the device complexity increases
Solution Approach 1:
The VCO circuit performs multiple functions using the same components: it generates the oscillation signal, provides supply noise sensing, and creates compensating signals all within a single integrated circuit structure. The differential pairs and current mirrors serve both as the core oscillation mechanism and as the noise compensation mechanism, eliminating the need for separate regulator circuits and reducing overall device complexity.
Solution Approach 2:
The patent merges the noise compensation function with the core VCO oscillation circuitry. The same differential transistor pairs and current mirrors that generate the oscillation are configured to simultaneously sense supply variations and produce compensating signals. This integration combines what would traditionally be separate functions into a unified circuit structure, reducing device complexity while improving power supply rejection.
3Device complexity
If supply voltage perturbations are allowed to pass through, then the circuit operates simply without compensation, but the jitter increases and bit error rate increases
Solution Approach 1:
The VCO circuit incorporates a feedback mechanism where the differential transistor pairs continuously monitor supply voltage variations and automatically generate compensating signals in response. This feedback loop detects supply noise and adjusts the circuit operation to counteract its effects, maintaining low jitter performance without requiring complex external regulation or sacrificing circuit simplicity.
Data Source
AI summary
High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.