CMOS-Compatible RRAM Stack With Interface Layers for Dense Arrays
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Solution Overview
Problem
Current RRAM devices fabricated on top interconnect layers face limitations in scaling down and increasing array density due to material and process incompatibilities with CMOS processes, leading to performance degradation under thermal, chemical, and mechanical stresses.
Innovation Solution
The development of CMOS-compatible RRAM devices fabricated on inner interconnect layers, incorporating a bottom electrode, switching oxide layer, top electrode, interface layers, diffusion barriers, and adhesion layers, with materials like Al2O3, TaN, and Ti4O7, to enhance scalability and resistance to annealing stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM devices are fabricated on top interconnect layers, then device integration is achieved, but scaling down and array density increase are limited due to material and process incompatibilities with CMOS processes
Solution Approach 1:
The patent introduces interface layers comprising chemically stable materials (such as Al2O3, MgO, Y2O3, or La2O3) that act as intermediaries between the RRAM device and the CMOS interconnect layers. These interface layers prevent harmful chemical reactions between the RRAM materials and subsequent CMOS fabrication processes, enabling RRAM devices to be integrated into CMOS processes while maintaining device performance and enabling scaling to higher array densities.
2Reliability
If RRAM devices are fabricated using standard processes, then manufacturing simplicity is maintained, but performance degradation occurs under thermal, chemical, and mechanical stresses
Solution Approach 1:
The patent applies preliminary protective actions by fabricating interface layers and diffusion barriers before subsequent CMOS interconnect fabrication processes. These protective layers are prepared in advance to prevent thermal, chemical, and mechanical stresses from damaging the RRAM device during later high-temperature annealing and metallization processes, thereby maintaining device reliability without requiring fundamental changes to the CMOS fabrication workflow.
Solution Approach 2:
The patent employs composite material structures consisting of multiple functional layers including interface layers made from chemically stable oxides (Al2O3, MgO, Y2O3, La2O3), diffusion barriers (TaN, TiN), and adhesion layers (Ti, Ta, Ti4O7). These composite structures provide simultaneous protection against thermal, chemical, and mechanical stresses while maintaining compatibility with standard CMOS processes, thus improving reliability without significantly increasing fabrication complexity.
3Reliability
If interface layers with chemically stable materials are added to protect RRAM devices, then resistance to annealing stresses is improved, but device structure complexity increases
Solution Approach 1:
The patent utilizes parameter changes by selecting materials with specific chemical stability properties (high thermal stability, low reactivity) for the interface layers. Materials such as Al2O3, MgO, Y2O3, and La2O3 are chosen because their chemical parameters (thermal stability, resistance to oxidation) provide inherent protection against annealing stresses. This approach improves reliability through material property optimization rather than increasing structural complexity, as the chemically stable materials naturally resist degradation under thermal processing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of RRAM devices within CMOS processes, improving scalability and enabling high-density memory and computing applications by maintaining performance resilience against subsequent fabrication stresses.
Implementation Method 1
a first interface layer fabricated between the top electrode and the switching oxide layer, where the first interface layer may include a first material that is more chemically stable than the at least one transition metal oxide
Implementation Method 2
The resistance of the RRAM device may be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying suitable programming signals to the RRAM device
Data Source
AI summary
An apparatus including a CMOS-compatible resistive random-access memory (RRAM) devices is provided. The apparatus includes a transistor; one or more first interconnect layers fabricated on the transistor; an RRAM device fabricated on the one or more first interconnect layers; and one or more second interconnect layers fabricated on the RRAM device. The RRAM device includes: a bottom electrode; a switching oxide layer including a transition metal oxide; a top electrode; and one or more interface layer including a material that is more chemically stable than the transition metal oxide. In some embodiments, one or more diffusion barriers and/or adhesion layers are fabricated between the RRAM device and the first interconnect layers and/or between the RRAM device and the second interconnect layers.