CMOS Scan Driver Stage Circuit Signal Integrity
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Solution Overview
Problem
The existing scan drivers face challenges with insufficient driving ability, leading to potential overlap and erroneous data voltage writing due to resistance-capacitance delays in scan signals, affecting the accuracy of pixel light emission in display devices.
Innovation Solution
The implementation of stage circuits as complementary metal oxide semiconductor (CMOS) circuits, including specific transistor configurations and inverter structures, enhances the driving ability by managing clock signals and power voltage lines to prevent signal overlap and improve current driving capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stage circuits are used in scan drivers, then device complexity is reduced, but driving ability becomes insufficient leading to signal overlap and erroneous data writing
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional stage circuits to CMOS circuits, fundamentally changing the circuit topology and operational parameters. The CMOS configuration with specifically sized transistors (first transistor larger than second transistor) and strategically placed capacitors changes the electrical parameters to achieve sufficient driving ability while preventing signal overlap.
Solution Approach 2:
The patent employs composite circuit design by combining multiple transistor types (first and second transistors with different sizes), capacitors, and clock signal sources into a unified CMOS stage circuit. This composite structure integrates multiple functional elements working together to provide both the driving capability and signal integrity required to resolve the contradiction.
2Productivity
If scan signals are transferred to multiple pixels, then coverage is improved, but resistance-capacitance delay increases causing signal overlap
Solution Approach 1:
The patent implements preliminary action through the first capacitor that pre-charges or pre-prepares the output node before the scan signal transition. This preliminary charging action compensates for the anticipated RC delay, ensuring that the signal arrives at multiple pixels within the required time window without overlap, thus maintaining productivity while reducing time loss.
Solution Approach 2:
The patent changes the electrical parameters of the stage circuit by using CMOS configuration with specifically sized transistors and added capacitors. This parameter change reduces the effective RC time constant of the signal path, allowing faster signal propagation to multiple pixels without causing overlap, thereby maintaining high productivity while reducing signal delay.
3Reliability
If stage circuit driving ability is increased, then signal overlap is prevented, but power consumption increases
Solution Approach 1:
The patent optimizes the power consumption by carefully selecting and sizing the transistors in the CMOS configuration. The first transistor is made larger than the second transistor to provide sufficient driving ability for signal integrity, while the overall CMOS structure and clock signal management minimize unnecessary power dissipation. This parameter optimization achieves the balance between reliability and energy efficiency.
Solution Approach 2:
The patent uses periodic clock signals to control the stage circuit operation, enabling the circuit to operate in a switched-mode fashion rather than continuously. This periodic activation reduces power consumption compared to continuously active circuits, while still maintaining sufficient driving ability and signal integrity during the active phases through proper transistor sizing and CMOS configuration.
Data Source
AI summary
A scan driver includes stage circuits, wherein each of the stage circuits includes a first transistor, wherein a first electrode thereof is coupled to a first node, a second electrode thereof is coupled to an input carry line, and a gate electrode thereof is coupled to a first clock line; and a capacitor, wherein a first electrode thereof is coupled to the first node and a second electrode thereof is coupled to a second node, wherein the second node is coupled to an output carry line, and the second node is selectively coupled to one of a first power voltage line and a second power voltage line.