CMOS Device Segmented Substrate for High Mobility
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Solution Overview
Problem
The integration of Group III-V materials and germanium with silicon substrates in semiconductor devices is limited by significant lattice constant and thermal expansion differences, leading to defects and performance limitations in CMOS devices.
Innovation Solution
Simultaneously forming a Group III-V compound semiconductor and a germanium base material on a silicon substrate, with specific transistor configurations and manufacturing methods that include forming substrates, electrodes, and gate structures to minimize defects and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Group III-V materials or Ge are integrated on a large-area silicon substrate, then manufacturing costs are lowered through general silicon manufacturing processes, but many defects occur at the interface due to large lattice constant difference and thermal expansion rate
Solution Approach 1:
The patent divides the substrate into multiple regions: a first substrate region with Group III-V compound semiconductor and a second substrate region with germanium semiconductor. This segmentation allows each material to be optimized independently while reducing interface defects by limiting the contact area between mismatched materials, thus maintaining manufacturing feasibility while improving interface quality.
Solution Approach 2:
The patent applies different semiconductor materials to different local regions of the substrate. The Group III-V material is used in regions requiring high electron mobility, while germanium is used in regions requiring high hole mobility. This local optimization allows each transistor type to have the most suitable material, improving overall device performance while managing material-silicon interface challenges.
2Reliability
If Group III-V materials or Ge are integrated on a large-area silicon substrate, then higher electron and hole mobility can be achieved, but many defects occur at the interface between these materials and silicon
Solution Approach 1:
The substrate is segmented into distinct first and second substrate regions, where the first region contains Group III-V compound semiconductor for n-type transistors and the second region contains germanium semiconductor for p-type transistors. This segmentation minimizes the total interface area between mismatched materials while preserving the high mobility benefits in each respective region.
Solution Approach 2:
The patent creates a composite substrate structure combining Group III-V compound semiconductor and germanium semiconductor on silicon. This composite approach allows leveraging the high electron mobility of Group III-V materials and high hole mobility of germanium, achieving superior overall device performance while managing interface challenges through careful material selection and regional optimization.
3Device complexity
If a single substrate material is used for both n-type and p-type transistors, then manufacturing simplicity is maintained, but device performance is limited by the inferior mobility characteristics of silicon
Solution Approach 1:
The patent implements local quality optimization by using Group III-V compound semiconductor in the first substrate region for n-type transistors to achieve high electron mobility, and germanium semiconductor in the second substrate region for p-type transistors to achieve high hole mobility. This regional material optimization significantly improves device performance while maintaining relatively simple manufacturing processes.
Solution Approach 2:
The patent employs a composite substrate architecture combining different semiconductor materials (Group III-V and germanium) on a silicon substrate. This composite structure enables each transistor type to benefit from the superior mobility characteristics of its optimized material, achieving high-performance CMOS devices with both n-type and p-type transistors exceeding silicon's mobility limitations.
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.