CMOS Sense Amplifier Staging to Reduce Line-Pair Interference
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Solution Overview
Problem
Semiconductor memory devices face signal interference between input and output line pairs due to their electrical connection, which affects the accuracy and efficiency of data sensing and amplification processes.
Innovation Solution
A CMOS latch-type sense amplifying circuit is introduced, featuring a CMOS differential amplifier and a CMOS latch-type sense amplifier, along with a common node controlled by an enable signal, to electrically separate input and output line pairs, reducing interference by amplifying signals in both pull-up and pull-down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the input line pair and output line pair are electrically connected in a conventional sense amplifier, then the amplification process can be simplified, but signal interference occurs between input and output lines reducing sensing accuracy
Solution Approach 1:
The sense amplifier is divided into two separate amplification stages: a first stage amplifier that amplifies the input line pair signal, and a second stage sense amplifier that amplifies the output line pair signal. This segmentation allows each amplifier to operate independently on its respective line pair, preventing signal interference while maintaining a relatively simple overall structure.
Solution Approach 2:
A switch circuit is introduced as an intermediary component between the first stage amplifier and the second stage sense amplifier. This switch circuit selectively couples or decouples the input line pair and output line pair based on operational phase, enabling the amplifiers to operate without direct electrical connection during sensitive operations, thus eliminating interference while preserving functionality.
2Measurement precision
If the input line pair and output line pair are electrically separated to reduce interference, then sensing accuracy improves, but the circuit structure becomes more complex
Solution Approach 1:
The circuit is segmented into distinct functional blocks: first stage amplifier, switch circuit, and second stage sense amplifier. Each block performs a specific function and can be independently optimized, which manages complexity while achieving the goal of electrical separation for improved sensing accuracy.
Solution Approach 2:
The switch circuit serves multiple functions: it couples the amplifiers during normal operation, decouples them during sensitive sensing phases, and enables phase-controlled operation. This multi-functionality reduces the need for additional dedicated components, thereby managing overall circuit complexity while achieving electrical separation when needed.
3Reliability
If a switch circuit is added to couple and decouple the line pairs, then signal interference is reduced, but the device complexity increases
Solution Approach 1:
The switch circuit is designed to perform multiple critical functions: coupling the amplifiers during operational phases, decoupling them during sensing phases to prevent interference, and enabling phase-controlled operation. By consolidating these functions into a single multi-functional component, the increase in device complexity is minimized while achieving reliable signal interference reduction.
Solution Approach 2:
The switch circuit acts as a controllable intermediary that dynamically manages the electrical connection between amplifiers. This intermediary approach allows the system to transition between coupled and decoupled states as needed, providing reliable interference reduction without requiring permanent or complex isolation structures.
Data Source
AI summary
A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.