CMOS Image Sensor Sample-and-Hold Circuit for Faster A/D Conversion
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Solution Overview
Problem
Related-art solid-state image sensing devices are slow in analog-to-digital (A/D) conversion operations.
Innovation Solution
A CMOS image sensor configuration with multiple sample-and-hold circuits is employed, where a first sample-and-hold circuit samples and holds a dark signal, and second to Mth sample-and-hold circuits sequentially sample and hold bright signals, enabling high-speed A/D conversion by alternately selecting and processing signals during each cycle period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single sample-and-hold circuit is used for A/D conversion, then the device complexity is low, but the A/D conversion speed is slow
Solution Approach 1:
The patent divides the sample-and-hold function into multiple parallel circuits (first sample-and-hold circuit for dark signal, second to Mth sample-and-hold circuits for bright signals). Each circuit processes different signal types simultaneously, enabling parallel processing and high-speed A/D conversion while managing complexity through functional segmentation
2Productivity
If multiple sample-and-hold circuits are used to process signals in parallel, then the A/D conversion speed increases, but the device complexity increases
Solution Approach 1:
The patent designs multiple sample-and-hold circuits that can be selectively activated based on signal type (dark or bright). The circuits share common A/D conversion resources and control logic, allowing the system to achieve high throughput for mixed signal types while avoiding the full complexity of always-active parallel processing
3Loss of time
If sequential processing of dark and bright signals is used, then the device complexity is low, but the loss of time increases
Solution Approach 1:
The patent enables continuous processing by having the first sample-and-hold circuit process dark signals while the second to Mth circuits simultaneously process bright signals. This parallel operation eliminates idle time between processing different signal types, achieving continuous useful action and reducing total processing time
Data Source
AI summary
Provided is a solid-state image sensing device that performs an A/D conversion operation at high speed. A sample-and-hold section 12 included in an A/D converter in a CMOS image sensor includes switches S1a and S1b and capacitor C1 that sample and hold a dark signal during each cycle period, switches S2a and S2b and capacitor C2 that sample and hold a bright signal during an odd-numbered cycle period, and switches S3a and S3b and capacitor C3 that sample and hold a bright signal during an even-numbered cycle period. While a bright signal is held with switch S2b placed in a conducting state, the next bright signal can be sampled by placing switch S3a in a conducting state.