CMOS Image Sensor ADC Layout for Kickback Noise Reduction
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Solution Overview
Problem
Conventional CMOS image sensors using ΔΣ modulation in A/D conversion circuits experience noise due to voltage fluctuations when the power supply cannot meet the instantaneous current requirements for parallel comparator operations, degrading image quality.
Innovation Solution
Implementing a system where different reference voltages are supplied to adjacent analog-to-digital conversion units within the CMOS image sensor to reduce noise by staggering the reference voltages used by comparators, thereby reducing kickback noise and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel actuation of comparators is implemented in ΔΣ A/D conversion circuits, then conversion speed and productivity are improved, but voltage fluctuations and noise occur due to instantaneous current requirements exceeding power supply capacity
Solution Approach 1:
The patent segments the comparators into multiple groups, each group receiving reference voltages with different phases. This segmentation allows the comparators to operate in staggered phases rather than all simultaneously, reducing the instantaneous current demand on the power supply while maintaining overall conversion throughput.
Solution Approach 2:
The patent implements periodic switching of reference voltages supplied to different comparator groups. By cycling through different reference voltage phases in a periodic manner, the system distributes the current demand over time, preventing voltage fluctuations while maintaining continuous conversion operation.
2Object-affected harmful factors
If multiple different reference voltages are supplied to adjacent analog-to-digital conversion units, then kickback noise is reduced and image quality is improved, but device complexity increases due to multiple supply units
Solution Approach 1:
The patent designs the supply units to be multi-functional, where each supply unit can provide multiple different reference voltage phases to different comparator groups. This universal design reduces the total number of supply units needed, as each unit performs multiple functions of providing different reference voltages to multiple comparators.
Solution Approach 2:
The patent pre-generates multiple reference voltage phases in advance using a small number of supply units, which then distribute these pre-prepared voltages to the comparator groups. This preliminary generation of reference voltages simplifies the overall architecture compared to generating separate reference voltages independently for each comparator.
Data Source
AI summary
An apparatus includes a plurality of analog-to-digital conversion units that performs analog-to-digital conversion using ΔΣ modulation by comparing a signal output from a plurality of pixels to a reference voltage; and a plurality of supply units that supply one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion units. The plurality of supply units supply different reference voltages to adjacent analog-to-digital conversion units among the plurality of analog-to-digital conversion units.