CMOS Image Sensor Contact Formation via Auxiliary Sidewalls
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Solution Overview
Problem
In CMOS image sensor manufacturing, reducing the drain ion implantation area increases the challenge of controlling junction capacitance, leading to unqualified product performance due to higher requirements for process precision in forming drain contacts.
Innovation Solution
A method involving the formation of auxiliary sidewalls on gate sidewalls, followed by the deposition of a silicide block layer, contact etch stop layer, and interlayer dielectric layer, with a photolithography process to define contact regions and etching processes that utilize a high etching selection ratio to form self-aligned source and drain contacts, ensuring they fall within the implantation region despite alignment deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the implantation area of drain ion implantation is decreased to reduce drain capacitance, then the signal of the photodiode is enhanced, but the requirement on process precision of drain contacts becomes higher
Solution Approach 1:
The patent introduces auxiliary sidewalls as intermediary structures formed on the gate sidewalls. These auxiliary sidewalls serve as mediating reference structures that enable more precise definition of the drain contact regions. By using these auxiliary sidewalls as alignment references during subsequent etching processes, the drain contacts can be more accurately positioned within the reduced implantation area, thus resolving the contradiction between reduced implantation area and contact alignment precision
Solution Approach 2:
The patent performs preliminary formation of auxiliary sidewalls and silicide block layers before defining the final contact regions. The auxiliary sidewalls are formed first to establish precise alignment references, followed by deposition of silicide block layers that define the contact material regions. This preliminary structuring enables subsequent photolithography and etching processes to achieve higher precision in contact formation, addressing the increased precision requirements when implantation area is reduced
2Reliability
If the implantation area of drain ion implantation is decreased to reduce drain capacitance, then the signal of the photodiode is enhanced, but the control of junction capacitance becomes more difficult
Solution Approach 1:
The auxiliary sidewalls act as intermediary structures that simplify the control of junction capacitance. By providing well-defined geometric boundaries, these auxiliary sidewalls enable more predictable and controllable ion implantation profiles and contact formation. The structured approach using auxiliary sidewalls as references reduces variability in the implantation process, making it easier to control the resulting junction capacitance values even when the implantation area is reduced
Solution Approach 2:
The patent changes the structural parameters by introducing auxiliary sidewalls with specific dimensions and materials. These parameter changes create a more controlled environment for ion implantation and contact formation. The auxiliary sidewalls define precise geometric boundaries that constrain the implantation process, enabling better control over the junction depth and area, thus simplifying the control of junction capacitance in reduced-implantation-area devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures that contacts are self-aligned with the source and drain, even with reduced implantation areas, thereby maintaining the performance of CMOS image sensors by controlling junction capacitance and ensuring precise contact formation.
Implementation Method 1
etching the silicide block layer by adopting a predetermined etching selection ratio to form source and drain contacts, wherein the etching rate of the silicide block layer is higher than the etching rate of the auxiliary sidewalls in the process of etching the silicide block layer
Implementation Method 2
performing a photolithography process to define source and drain contact regions
Implementation Method 3
performing source and drain ion implantation processes on the two sides of the transmission gate structure to form source and drain
Data Source
AI summary
A method for forming contacts applied to a CMOS image sensor includes: forming a transmission gate structure; performing source and drain ion implantation processes to form source and drain; forming auxiliary sidewalls on the outer sides of the gate sidewalls, the material of the auxiliary sidewalls being the same as the material of the adjacent gate sidewalls; sequentially forming a silicide block layer, a contact etch stop layer and an interlayer dielectric layer; defining source and drain contact regions; performing etching processes to remove the interlayer dielectric layer and the contact etch stop layer corresponding to the source and drain contact regions sequentially; etching the silicide block layer by adopting a predetermined etching selection ratio to form source and drain contacts, wherein the etching rate of the silicide block layer is higher than the etching rate of the auxiliary sidewalls in the process of etching the silicide block layer.