CMOS Image Sensor Doping Profile for Leak Control and Linearity

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Solution Overview

Problem

Conventional solid-state image capturing apparatuses face issues with crystal defects and stress defects near element separation sections, leading to leak currents and uneven display irregularities, which are difficult to correct using digital processing, and the back bias effect affects the output characteristics of source follower circuits.

Innovation Solution

A solid-state image capturing apparatus with a semiconductor substrate where the amplifying transistor has a distinct impurity concentration profile different from that of the peripheral circuit transistors, and a leak stopper is used to prevent leak currents, allowing independent setting of the amplifying transistor's concentration profile and improving the source follower circuit's linearity and dynamic range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a leak stopper is formed near the element separation section to prevent leak currents, then display uniformity is improved, but the impurity concentration in the pixel region increases causing back bias effect and deteriorating source follower circuit characteristics

Engineering Contradiction:
Improvedisplay uniformityVSAvoidsource follower circuit characteristics
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent divides the semiconductor substrate into distinct regions with different impurity concentration profiles: a first region for the amplifying transistor with lower impurity concentration and a second region for the leak stopper with higher impurity concentration. This segmentation allows the leak stopper to prevent display uniformity issues while the amplifying transistor region maintains optimal characteristics for source follower circuits by avoiding excessive back bias effect.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating spatially varying impurity concentration profiles across different functional regions. The amplifying transistor region has a first impurity concentration profile optimized for analog signal processing, while the leak stopper region has a second impurity concentration profile optimized for preventing leak currents. This local optimization resolves the contradiction between display uniformity and circuit characteristics.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the impurity concentration profile is uniformly set across the substrate, then manufacturing process is simplified, but the back bias effect cannot be independently controlled for pixel transistors

Engineering Contradiction:
Improveion implantation processVSAvoidback bias effect control
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements local quality through region-specific impurity concentration profiles. The amplifying transistor region receives a first ion implantation treatment with specific concentration and depth parameters, while the leak stopper region receives a second treatment with different parameters. This allows independent optimization of back bias effect for pixel transistors while maintaining manufacturing feasibility through sequential processing steps.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying impurity concentration, implantation depth, and doping type across different regions. The amplifying transistor region has controlled impurity parameters to minimize back bias effect, while the leak stopper region has higher impurity concentration to prevent leak currents. These parameter variations enable independent control of electrical characteristics without fundamentally changing the manufacturing process flow.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively controls the back bias effect, improves the linearity of the source follower circuit, and expands the dynamic range by simplifying the ion implantation process and preventing leak currents, thus enhancing the output characteristics and correcting display irregularities.

Implementation Method 1

a pixel light receiving section (photodiode) for converting incident light into a signal charge by photoelectric conversion

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Implementation Method 2

a second-conductivity type semiconductor region, in which the amplifying transistor is formed, having an impurity concentration profile different from an impurity concentration of a second-conductivity type semiconductor region, in which a peripheral circuit transistor that constitutes the peripheral circuit is formed

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20090242741A1Solid-state image capturing apparatus, manufacturing method for the solid-state image capturing apparatus, and electronic information device
Publication Date: 2009.10.01 RS TECH CO LTD
  • US20090242741A1 patent drawing
  • US20090242741A1 patent drawing
  • US20090242741A1 patent drawing

AI summary

A solid-state image capturing apparatus is provided, where each of the pixels comprises a pixel light receiving section for converting incident light into a signal charge by photoelectric conversion, a charge storing section for storing the signal charge and generating a signal voltage in accordance with the stored signal charge, and an amplifying transistor for amplifying and outputting the signal voltage. A second-conductivity type semiconductor region, in which the amplifying transistor is formed, on the semiconductor substrate has an impurity concentration profile different from an impurity concentration profile of a different second-conductivity type semiconductor region, in which a peripheral circuit transistor that constitutes the peripheral circuit is formed.