CMOS Image Sensor DVFS Circuit for Intra-Frame Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Imaging devices face challenges in reducing power consumption, particularly in always-on and viewing modes where power is wasted during the V-blanking and integration periods due to unnecessary high clock frequencies and voltages.
Innovation Solution
The implementation of dynamic voltage frequency scaling (DVFS) within one-frame operations in CMOS image sensors, where the clock frequency and voltage are dynamically adjusted using a regulator and switch in parallel configuration, allowing for intra-frame DFS and DVS, reducing power consumption by operating selective blocks with low-frequency clock signals and lower voltages during idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the imaging device operates continuously in always-on and viewing modes, then the imaging function is maintained, but power consumption increases due to idle period waste
Solution Approach 1:
The patent applies dynamic voltage frequency scaling (DVFS) to make the operating voltage and frequency of the imaging device variable rather than fixed. The regulator dynamically adjusts the output voltage based on operational mode, and the clock frequency is scaled accordingly. This allows the system to transition between high-performance modes (full frequency and voltage during active imaging) and low-power modes (reduced frequency and voltage during idle periods like V-blanking and integration periods), thereby resolving the contradiction between maintaining imaging availability and reducing power consumption.
2Use of energy by moving object
If the clock frequency is reduced during idle periods, then power consumption decreases, but imaging performance may be affected
Solution Approach 1:
The patent implements periodic action by alternating between high-frequency operation during active imaging periods and low-frequency operation during idle periods (V-blanking and integration periods). The clock frequency is periodically scaled down during these idle periods when no imaging processing is required, and then restored to full frequency when imaging resumes. This periodic modulation of frequency allows the system to accumulate significant power savings over time while maintaining full imaging performance when needed, as the idle periods are naturally occurring gaps in the imaging cycle.
3Use of energy by moving object
If the voltage is lowered during idle periods, then power consumption is reduced, but signal integrity may deteriorate
Solution Approach 1:
The patent applies local quality by selectively lowering voltage only in specific circuits and during specific time periods rather than uniformly across the entire system. The regulator provides different voltage levels to different functional blocks based on their current operational state. During idle periods, voltage is reduced only in blocks that are not actively processing imaging data, while blocks that may need to maintain state or prepare for upcoming operations receive appropriate voltage levels. This localized voltage scaling maintains signal integrity in critical paths while achieving power savings in non-critical areas.
Data Source
AI summary
An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.