CMOS Image Sensor Digital Double Sampling With Inverted Up-Counter

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Solution Overview

Problem

Conventional CMOS image sensors with up-down counters face challenges due to a large number of gates and high power consumption, especially in high-resolution image sensors, which limits their efficiency and area occupancy.

Innovation Solution

A digital double sampling method using a counter that operates in the two's complement number system, inverting digital data and counting in synchronization with a clock signal, reduces the number of gates and power consumption by performing the functions of an up-down counter with a counter that counts in only one direction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an up-down counter is used to perform digital double sampling, then the digital double sampling function is achieved, but the number of gates increases and the circuit area becomes large

Engineering Contradiction:
Improvedigital double sampling functionVSAvoidnumber of gates
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies inversion by using a single up-counter instead of a traditional up-down counter. The counter counts upward from an initial value that is set to the inverted (complementary) value of the reset level. This inversion of the counting direction and initial value setup allows the circuit to achieve digital double sampling functionality with fewer gates, directly resolving the contradiction between functional reliability and device complexity.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If an up-down counter is used to perform digital double sampling, then the digital double sampling function is achieved, but power consumption increases

Engineering Contradiction:
Improvedigital double sampling functionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent reduces power consumption by inverting the approach from using an up-down counter to using a single up-counter with an inverted initial value. The up-counter requires fewer switching operations and has simpler circuit logic, which directly reduces dynamic power consumption while maintaining the digital double sampling function. This inversion strategy effectively resolves the contradiction between functional reliability and energy usage.

Inventive Principle:
Principle #13The other way round (Inversion)

3Measurement precision

If high resolution imaging is implemented, then image quality is improved, but power consumption becomes more limited

Engineering Contradiction:
Improveimage resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent enables high-resolution imaging with reduced power consumption by inverting the counter design approach. The simplified up-counter with inverted initial value reduces the power consumption per pixel, allowing high-resolution sensors to operate within power constraints. This inversion of the counting mechanism provides a scalable solution that maintains image quality while addressing power limitations in high-resolution applications.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS7995123B2Digital double sampling method, a related CMOS image sensor, and a digital camera comprising the CMOS image sensor
Publication Date: 2011.08.09 SAMSUNG ELECTRONICS CO LTD
  • US7995123B2 patent drawing
  • US7995123B2 patent drawing
  • US7995123B2 patent drawing

AI summary

A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.