CMOS Sensor Multi-Pixel Sharing with 3D Stacked Voltage Conversion
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Solution Overview
Problem
Conventional multi-pixel sharing structures in CMOS sensors face challenges in reducing pixel size while ensuring sufficient area for photoelectric conversion elements and maintaining uniform optical center spacing, leading to poor design flexibility and reduced signal charge accumulation.
Innovation Solution
A solid-state imaging device with a multi-pixel sharing structure where voltage conversion elements are arranged between diagonally adjacent photoelectric conversion elements, effectively utilizing free space and ensuring the photoelectric conversion elements are allocated to the optical center of each pixel, allowing for equal two-dimensional spacing of optical pixel centers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If component transistors are shared between multiple pixels to reduce pixel size, then area occupancy is reduced, but uniform arrangement of photoelectric conversion elements and equal spacing of optical centers cannot be achieved
Solution Approach 1:
The pixel array is divided into multiple banks, with each bank containing photoelectric conversion elements and associated circuitry. This segmentation allows independent optimization of each bank while maintaining overall uniformity and equal spacing of optical centers across the entire array.
Solution Approach 2:
The patent transitions from conventional two-dimensional sharing to three-dimensional stacking, placing photoelectric conversion elements, circuit layers, and interconnect structures in multiple vertical layers. This enables uniform horizontal spacing while utilizing vertical space for component placement, resolving the conflict between area reduction and uniform arrangement.
2Area of stationary object
If transistor area is reduced to increase photoelectric conversion element area, then pixel area is reduced, but design flexibility deteriorates due to narrow spacing requirements
Solution Approach 1:
By moving to three-dimensional stacking, the patent decouples horizontal and vertical dimensions. Photoelectric conversion elements can be enlarged in the horizontal plane without proportionally increasing transistor area, as transistors and interconnects are placed in vertical layers, thereby maintaining design flexibility while increasing photoelectric conversion area.
Solution Approach 2:
The patent implements shared circuitry that serves multiple photoelectric conversion elements across different banks and layers. This multi-functional design allows a single transistor or interconnect structure to support multiple pixels, reducing overall transistor area while maintaining adequate spacing and design flexibility.
3Area of stationary object
If multi-pixel sharing structure is implemented, then pixel size is reduced, but signal charge accumulation is reduced
Solution Approach 1:
The three-dimensional stacking architecture allows photoelectric conversion elements to be positioned in multiple vertical layers, each capable of independent charge accumulation. This enables reduced horizontal pixel size while maintaining sufficient charge accumulation capacity through vertical stacking of photoelectric conversion elements and associated circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement increases the area for photoelectric conversion elements, improves dynamic range, reduces random noise, and enhances image quality by increasing the amount of signal charge, while enabling high-speed signal readout and efficient use of space.
Implementation Method 1
photoelectric conversion elements arranged in a two-dimensional array and voltage conversion elements for converting charge, produced by photoelectric conversion through the photoelectric conversion elements
Data Source
AI summary
A solid-state imaging device with a multi-pixel sharing structure, wherein the area of each photoelectric conversion element can be secured independent of a reduction in area of each pixel. A solid-state imaging device including photoelectric conversion elements arranged in a two-dimensional array and voltage conversion elements for converting charge produced by photoelectric conversion through the corresponding photoelectric conversion elements into voltage.