CMOS Image Sensor Readout Circuit With Orthogonal Data Transfer
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Solution Overview
Problem
CMOS image sensors face challenges in high-speed signal reading due to limited layout space, leading to long column reading circuits, increased wiring capacitance and resistance, and noise interference from shared data transfer signal lines, which degrade operation speed and increase power consumption.
Innovation Solution
The implementation of a pixel-signal reading circuit with cascade-connected counters and latches, where first switches connect bit outputs to a column-signal transfer line and second switches connect latch outputs to orthogonal data transfer signal lines, allowing for orthogonal data transfer and reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixels are miniaturized and arranged densely to increase pixel count, then image resolution is improved, but layout space for reading circuits becomes limited
Solution Approach 1:
The patent transitions data transfer from a primarily vertical direction to include orthogonal (horizontal) directions. By enabling data to be transferred in multiple spatial dimensions through the column-signal transfer line, the circuit accommodates dense pixel arrangements without requiring excessive vertical space, thus resolving the contradiction between pixel density and available layout area.
2Productivity
If column reading circuits are extended to handle more pixels, then signal reading capability is improved, but wiring capacitance and resistance increase
Solution Approach 1:
The patent segments the data transfer path by introducing a column-signal transfer line that collects signals from multiple counters. Instead of having each counter independently connect to output circuits over long distances, the segmentation approach groups signals locally and transfers them collectively, reducing individual wiring lengths and associated capacitance and resistance losses.
Solution Approach 2:
Multiple counter outputs are merged into a shared column-signal transfer line. By combining multiple signal paths into a single orthogonal transfer line, the patent reduces the total number of long vertical connections required, thereby decreasing overall wiring capacitance and resistance while maintaining signal reading capability.
3Device complexity
If shared data transfer signal lines are used to reduce circuit complexity, then device complexity is reduced, but noise interference increases
Solution Approach 1:
The patent extracts the data transfer function from the vertical column paths and places it in a dedicated orthogonal column-signal transfer line. By separating the transfer function into a distinct orthogonal path, the design reduces noise interference on individual vertical lines while maintaining the benefits of shared transfer infrastructure, thus taking out the harmful noise aspect while preserving circuit simplicity.
4Speed
If high-speed reading is implemented to meet processing requirements, then signal reading speed is improved, but power consumption increases
Solution Approach 1:
By introducing orthogonal data transfer paths, the patent enables faster signal evacuation from the pixel array without requiring excessively long vertical paths that would demand higher drive currents. The orthogonal dimension provides additional routing options that reduce signal travel distance and associated power consumption while maintaining high reading speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables low power consumption and high-speed counter operation while minimizing noise-induced data transfer errors, improving the efficiency of signal processing and image quality.
Implementation Method 1
a pixel section including a plurality of pixels arranged in a matrix, the plurality of pixels performing photoelectric conversion
Data Source
AI summary
A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.