Layered CMOS Image Sensor Pads for Known Good Die Inspection
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Solution Overview
Problem
Conventional manufacturing methods for solid-state imaging elements lack inspection capabilities for semiconductor substrates without dedicated inspection pads, hindering the production of conforming products.
Innovation Solution
A solid-state imaging element with a first semiconductor substrate having a pad for external connection and a second semiconductor substrate with a dedicated inspection pad, where the pads are electrically connected via electrodes, allowing for inspection and bonding of both substrates to ensure known good die (KGD) quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If inspection pads are not provided for some semiconductor substrates, then device complexity is reduced, but manufacturing precision deteriorates because inspection for known good die cannot be performed
Solution Approach 1:
The first pad on the second semiconductor substrate serves multiple functions: it acts as an external connection pad for signal input/output and simultaneously serves as an inspection pad for known good die inspection. This multi-functional design eliminates the need for separate dedicated inspection pads, resolving the contradiction between device complexity and manufacturing precision.
2Manufacturing precision
If separate dedicated inspection pads are provided, then manufacturing precision is improved by enabling thorough inspection, but device complexity increases
Solution Approach 1:
The invention makes the first pad serve dual purposes: external electrical connection and inspection functionality. By integrating these two functions into a single pad structure, the patent achieves thorough inspection capability without adding separate dedicated inspection pads, thus maintaining simple device structure while improving manufacturing precision.
3Reliability
If pads are electrically connected via electrodes between substrates, then reliability is improved by ensuring known good die quality, but device complexity increases due to additional connection structures
Solution Approach 1:
The patent performs inspection of the second semiconductor substrate before bonding to the first substrate by measuring the electrical continuity between the first pad and second pad through the electrodes. This preliminary inspection action ensures that only known good die are bonded together, improving reliability while using the existing electrode structures without adding extra complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of more conforming products by ensuring thorough inspection and bonding of both substrates, reducing parasitic resistance and capacitance, and improving wire bond resistance.
Implementation Method 1
the first pad and the second pad are electrically connected to each other via a first electrode provided in the first semiconductor substrate and a second electrode provided in the second semiconductor substrate
Data Source
AI summary
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus capable of manufacturing more conforming products. A first semiconductor substrate is provided with a first pad used for connection with the outside, separately from a dedicated pad used for inspection in a manufacturing process. A second semiconductor substrate is provided with a second pad used for inspection in a manufacturing process. Then, when the first semiconductor substrate and the second semiconductor substrate are layered in units of chips after inspection for guaranteeing KGD is performed on each of the first semiconductor substrate and the second semiconductor substrate, the first pad and the second pad are electrically connected to each other via a first electrode provided in the first semiconductor substrate and a second electrode provided in the second semiconductor substrate. The present technology can be applied to a layered CMOS image sensor, for example.