Backside CMOS Image Sensor Pad Layout With Through-Hole Exposure
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Solution Overview
Problem
In back side illumination type solid-state image pickup elements, forming pads in specific locations is challenging due to surface undulations in the semiconductor layer, which affects light condensing characteristics and high-temperature process limitations, leading to potential quality reduction and increased contact resistance.
Innovation Solution
A solid-state image pickup element with a pixel substrate having a light condensing layer, semiconductor layer, and wiring layer laminated together, where at least a part of the pad is exposed through a through hole completely extending through the light condensing and semiconductor layers, allowing for external connection and reducing surface irregularities and temperature limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the pad is formed on the upper surface of the wiring in the uppermost layer of the wiring layer of the pixel substrate, then the position of the pad becomes shallow and easier to access, but surface undulations are generated on the semiconductor layer making it difficult to uniformly form coating films
Solution Approach 1:
The invention divides the pad formation process into two independent parts: (1) forming the pad on the upper surface of the uppermost wiring layer, and (2) separately planarizing the semiconductor layer surface. This segmentation allows the pad to be positioned shallowly for easy accessibility while the semiconductor layer surface is independently planarized to ensure uniform coating film formation, thus resolving the technical contradiction between pad accessibility and coating film uniformity.
Solution Approach 2:
The invention applies preliminary planarization treatment to the semiconductor layer surface before forming coating films such as color filters and microlenses. By pre-flattening the semiconductor layer surface, the invention ensures that subsequent coating films can be uniformly formed even when pads are positioned shallowly on the wiring layer, thereby resolving the contradiction between pad accessibility and coating uniformity.
2Ease of operation
If the pad is formed in the semiconductor layer, then the position of the pad becomes shallow, but high-temperature process limitations are caused affecting semiconductor element characteristics
Solution Approach 1:
The invention moves the pad formation location from the semiconductor layer to the wiring layer, which is a different dimensional level above the semiconductor layer. This dimensional change allows the pad to be positioned shallowly for accessibility while the high-temperature semiconductor element formation process can proceed without being constrained by pad formation temperature limitations, thus resolving the contradiction between pad accessibility and semiconductor element characteristics.
3Temperature
If the interlayer film is thickened to planarize the trench for pad formation, then the temperature limitation in high-temperature process is avoided, but contact resistance of the wiring layer increases
Solution Approach 1:
The invention extracts the pad formation process from the semiconductor layer and relocates it to the wiring layer. This extraction eliminates the need to thicken the interlayer film for planarization purposes, as the pad is now formed on the already-planarized upper surface of the wiring layer. Consequently, the high-temperature process capability is maintained while avoiding the increase in contact resistance that would result from thickening the interlayer film.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables pads to be formed in suitable positions without compromising the quality of the back side illumination type solid-state image pickup element, improving light condensing characteristics and reducing high-temperature process constraints, thus enhancing the overall performance.
Implementation Method 1
a light condensing layer for condensing incident light on a photoelectric conversion element
Data Source
AI summary
The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.