CMOS Image Sensor Read-Out Architecture Without Differential Buffers

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Solution Overview

Problem

Conventional CMOS image sensors face challenges with high power consumption and noise due to the need for two buffers in the output channel, leading to gain mismatch errors and increased complexity in design, especially in achieving high common-mode rejection ratio (CMRR) for reducing fixed pattern noise.

Innovation Solution

A multiplexed read-out architecture that eliminates the dedicated time frame for the reference level, allowing direct extraction of the reference level from pixel VN and VNS signals, reducing the circuit to a single level and eliminating the need for differential structures, thereby simplifying the design and reducing noise and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two buffers are used to read pixel offset and signal levels separately, then the pixel offset and signal can be read sequentially, but the power consumption and noise increase

Engineering Contradiction:

Improvepixel offset and signal reading accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the reading of pixel offset and signal levels into a single buffer by implementing sequential reading operations. The buffer is first used to read the pixel offset level, then the same buffer reads the pixel signal level, eliminating the need for separate buffers and reducing power consumption while maintaining reading accuracy.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single buffer is designed to perform multiple functions: it serves as both the offset reading buffer and the signal reading buffer. By making the buffer universal, the patent reduces the total number of buffers from two to one, thereby halving the power consumption associated with buffer operations while preserving the ability to accurately read both offset and signal levels.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If two buffers are used for reading offset and signal levels, then sequential reading is enabled, but the noise increases due to multiple buffer operations

Engineering Contradiction:

Improvepixel offset and signal reading accuracyVSAvoidnoise

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent combines the offset and signal reading operations into a single buffer, reducing the number of buffer operations from two to one. This merging eliminates the additional noise that would be generated by a second buffer, while the sequential reading process maintains the accuracy of both offset and signal level readings.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If differential amplifiers and two buffers are used, then pixel offset and signal can be read, but gain mismatch errors and fixed pattern noise are introduced

Engineering Contradiction:

Improvepixel offset and signal reading accuracyVSAvoidgain matching accuracy

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts and eliminates the differential amplifier from the reading circuitry by implementing a single-buffer reading approach. By removing the differential amplifier, the patent eliminates the source of gain mismatch errors and fixed pattern noise that arise from imperfect matching between the two buffers, while still enabling accurate reading of both pixel offset and signal levels through sequential operations.

Inventive Principle:

Principle #2Taking out (Extraction)

4Object-affected harmful factors

If differential structures are used for reading, then interference rejection is achieved, but the circuit complexity and power consumption increase

Engineering Contradiction:

Improveinterference rejectionVSAvoidcircuit complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts and removes the differential structure from the reading circuitry by implementing a single-buffer sequential reading approach. This eliminates the complex differential amplifier circuit while maintaining interference rejection through the use of correlated double sampling, thereby reducing circuit complexity and power consumption without sacrificing the ability to reject common-mode interference.

Inventive Principle:

Principle #2Taking out (Extraction)

5Object-affected harmful factors

If differential amplifiers are used, then interference rejection is achieved, but power consumption increases

Engineering Contradiction:

Improveinterference rejectionVSAvoidpower consumption

Core Design Contradiction:

Object-affected harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent extracts and eliminates the differential amplifier from the circuit by implementing a single-buffer reading approach. This removal eliminates the high power consumption associated with differential amplifiers while maintaining interference rejection capabilities through correlated double sampling, thereby achieving a power-efficient solution that does not sacrifice interference rejection performance.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8976273B2Multiplexed read-out architecture for CMOS image sensors

Publication Date: 2015.03.10 TEXAS INSTRUMENTS INC

AI summary

This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.