CMOS Image Sensor Superlattice Channel for Mobility and Thermal Management
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Solution Overview
Problem
Current semiconductor devices lack enhanced performance in terms of charge carrier mobility and thermal management, despite existing advancements in strained material layers and superlattice structures.
Innovation Solution
The implementation of a superlattice structure in CMOS image sensors, comprising stacked groups of semiconductor monolayers with non-semiconductor monolayers constrained within the crystal lattice, which reduces the effective mass of charge carriers and enhances mobility, while also acting as a barrier to dopant diffusion and providing improved energy band engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers (silicon-germanium) are used to enhance charge carrier mobility, then device speed and performance are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent changes the structural parameters of the semiconductor layer by introducing a superlattice configuration with alternating monolayers of different materials (e.g., SiGe and SiC) rather than using uniform strained silicon-germanium layers. This structural parameter change achieves mobility enhancement through a different mechanism (band structure engineering) while potentially simplifying the manufacturing process by using sequential deposition of distinct layers rather than precise control of alloy composition and strain.
2Temperature
If conventional semiconductor structures are used, then manufacturing process is simpler, but thermal management performance is insufficient
Solution Approach 1:
The patent employs composite material structures by creating superlattice channels with alternating monolayers of different semiconductor materials (e.g., SiGe/SiC, Si/SiC). These composite structures provide both mechanical strain for mobility enhancement and thermal conduction pathways through the carefully selected material combinations, thereby improving thermal management while maintaining structural integrity.
3Speed
If superlattice structures with multiple monolayers are implemented, then charge carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the semiconductor channel into distinct alternating monolayers of different materials, where each monolayer can be deposited separately using epitaxial growth techniques. This segmentation allows for better control of each individual layer's thickness and composition, reducing the cumulative precision errors that would occur in continuous alloy growth, while still achieving the desired mobility enhancement through the superlattice configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher charge carrier mobility, reduced scattering effects, and improved thermal management, leading to enhanced performance and efficiency in CMOS image sensors.
Implementation Method 1
The superlattice channel may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
The superlattice channel may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Data Source
AI summary
A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.