CMOS Image Sensor Superlattice Crosstalk Reduction
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Solution Overview
Problem
Current semiconductor devices, such as CMOS image sensors, face limitations in charge carrier mobility and crosstalk between pixels, which affect their performance and efficiency.
Innovation Solution
The implementation of a superlattice structure on a semiconductor substrate with stacked groups of layers, including semiconductor and non-semiconductor monolayers, enhances charge carrier mobility and reduces crosstalk by modifying energy band structures and providing improved retrograde well profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is limited
Solution Approach 1:
The semiconductor layer is segmented into multiple alternating monolayers of different materials (e.g., Si/SiGe/SiC) to form a superlattice structure. This segmentation creates distinct regions with different band gaps and effective masses, enabling enhanced charge carrier mobility through quantum confinement effects and reduced scattering while maintaining a manageable manufacturing process
Solution Approach 2:
The patent employs composite material structures where alternating layers of semiconductor materials with different properties (Si, SiGe, SiC) are combined to form a superlattice. This composite approach leverages the advantageous properties of each material to achieve higher charge carrier mobility than any single material could provide alone
2Reliability
If standard semiconductor layers are used, then structure is simpler, but crosstalk between pixels occurs
Solution Approach 1:
The superlattice structure introduces local variations in material composition and band structure at the pixel level. By creating regions with different effective masses and band gaps in alternating monolayers, the structure provides localized quantum confinement that prevents charge carrier diffusion between adjacent pixels, thereby reducing crosstalk while maintaining overall device functionality
Solution Approach 2:
The alternating monolayers in the superlattice act as intermediary barriers between adjacent pixel regions. These intermediate layers with different material properties create potential barriers that block charge carrier diffusion pathways, preventing crosstalk without requiring direct physical isolation structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure achieves higher charge carrier mobility and reduced crosstalk between adjacent pixels, leading to improved performance in CMOS image sensors by lowering conductivity effective mass and acting as a barrier to dopant and material diffusion.
Implementation Method 1
enhances charge carrier mobility and reduces crosstalk by modifying energy band structures
Implementation Method 2
The superlattice structure achieves higher charge carrier mobility and reduced crosstalk between adjacent pixels, leading to improved performance in CMOS image sensors by lowering conductivity effective mass
Implementation Method 3
acting as a barrier to dopant and material diffusion
Data Source
AI summary
A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.