CMOS Image Sensor Charge Transfer With V-NW Transistors
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Solution Overview
Problem
Existing CMOS image sensors face limitations in reducing read noise and dark current due to the capacitance of the PN junction at the floating diffusion layer, which also restricts the suppression of read noise and introduces leakage currents.
Innovation Solution
The use of Vertical Nano Wire (V-NW) transistors in a solid-state image pickup apparatus, eliminating the PN junction in the charge accumulation section and incorporating a wiring layer to reduce capacitance, thereby minimizing read noise and dark current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PN junction is used to form the floating diffusion layer for charge accumulation, then the charge can be accumulated effectively, but the capacitance of the PN junction increases read noise and cannot be reduced sufficiently
Solution Approach 1:
The patent extracts and removes the PN junction structure from the charge accumulation section. By replacing the traditional PN junction-based floating diffusion layer with a simplified charge accumulation section that directly accumulates charge without requiring a PN junction, the source of junction capacitance (which causes read noise) is eliminated while charge accumulation functionality is preserved
Solution Approach 2:
The patent changes the fundamental parameter of the charge accumulation mechanism by transitioning from a PN junction-based system (with inherent junction capacitance) to a direct charge accumulation system. This parameter change eliminates the capacitance-related read noise while maintaining charge accumulation capability
2Reliability
If a PN junction is used to form the floating diffusion layer, then charge accumulation is achieved, but leakage current occurs between P-type and N-type areas causing dark current generation
Solution Approach 1:
The patent removes the P-N junction structure that is the source of leakage current. By eliminating the junction between P-type and N-type semiconductor regions, the leakage current path is removed, thereby preventing dark current generation while alternative charge accumulation methods are employed
3Ease of manufacture
If planar transistors are used in the CMOS image sensor, then the device can be manufactured with conventional processes, but the transistor area is large and capacitance is high
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. By stacking transistor layers vertically, the transistor functionality is achieved in a smaller footprint area on the substrate, reducing the overall device area while maintaining manufacturability through extended fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces read noise and dark current, enhances the area efficiency of the photoelectric conversion section, and improves light sensitivity by minimizing transistor size and capacitance.
Implementation Method 1
a photoelectric conversion section that generates and holds a charge in response to incident light
Data Source
AI summary
A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.