CMOS Shift Register Circuit for Low-Power High-Definition Displays
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Solution Overview
Problem
Conventional active matrix liquid crystal display devices face challenges in achieving high definition due to increased transistor elements, high power consumption, reliability issues with p-type and n-type MOS transistors, and difficulty in reducing clock amplitude and voltage while maintaining high-speed operation.
Innovation Solution
A CMOS shift register circuit is designed with a simple CMOS circuit structure, utilizing seven transistors formed from poly-silicon thin film transistors, where the clock is applied to the source of n-type MOS transistors, and the input signal is applied to the gate of both n-type and p-type MOS transistors, reducing load capacitance and power consumption by optimizing transistor operation and eliminating the need for a level shifter circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of transistor elements is increased to achieve high definition, then the display quality is improved, but the power consumption is increased and the circuit complexity is increased
Solution Approach 1:
The patent changes the operating parameters of the shift register circuit by applying the clock signal to the source of n-type MOS transistors rather than the gate, and by optimizing the transistor sizing and configuration. This parameter change enables the circuit to achieve high-definition display quality with reduced power consumption by minimizing unnecessary current flow while maintaining the required switching performance for high-resolution displays.
Solution Approach 2:
The patent applies different configurations to different parts of the circuit: n-type MOS transistors are used for clock switching at the source terminal, while p-type MOS transistors are used for signal inversion at the gate terminal. This local differentiation optimizes each transistor's function for its specific role, reducing overall power consumption while maintaining high display quality.
2Speed
If p-type and n-type MOS transistors are operated for every clock to achieve high-speed operation, then the operation speed is improved, but the reliability is deteriorated due to remarkable transistor deterioration
Solution Approach 1:
The patent implements periodic action by using the clock signal to alternately control the n-type MOS transistors in a rhythmic manner, enabling high-speed operation during active periods while allowing transistors to rest during inactive periods. This periodic operation reduces cumulative stress on transistors, improving reliability while maintaining high operation speed when needed.
Solution Approach 2:
The circuit design allows transistors to self-regulate their operation through the clocked configuration, where the clock signal automatically controls when transistors switch on and off. This self-service mechanism optimizes the balance between speed and reliability without requiring external intervention, reducing deterioration while maintaining high-speed performance.
3Use of energy by stationary object
If the clock amplitude is reduced to achieve low power consumption, then the power consumption is reduced, but the high-speed operation capability is compromised
Solution Approach 1:
The patent changes the critical parameter of clock application from gate voltage to source voltage control. By applying the clock signal to the source of n-type MOS transistors, the circuit achieves efficient switching with lower clock amplitude, reducing power consumption while maintaining high operation speed through optimized transistor channel control.
4Adaptability or versatility
If a level shifter circuit is added to convert voltage levels, then the voltage level conversion is achieved, but the device complexity and power consumption are increased
Solution Approach 1:
The patent merges the voltage level conversion function directly into the shift register circuit by using the p-type MOS transistors configured as inverters that naturally produce the required voltage level transitions. This integration eliminates the need for separate level shifter circuits, reducing device complexity and power consumption while maintaining the necessary voltage level adaptability for high-definition display operation.
Solution Approach 2:
The p-type MOS transistors in the circuit serve multiple functions: they act as signal inverters for the shift register operation and simultaneously provide voltage level conversion. This multi-functionality eliminates the need for dedicated level shifter components, reducing overall circuit complexity while achieving the required voltage level adaptation.
Data Source
AI summary
The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n≧2) pieces of basic circuits which are connected vertically in multiple stages. The basic circuit includes a first transistor of a first conductive type having a first electrode to which a clock is applied, a second transistor of a second conductive type different from the first conductive type in a conductive type and having a first electrode to which a second power source voltage is applied, and a third transistor of a first conductive type having a second electrode which is connected to the second electrode of the second transistor and a first electrode to which a first power source voltage different from the second power source voltage is applied, wherein the second electrode of the first transistor is connected to a control electrode of the third transistor, an input signal is applied to a control electrode of the first transistor and a control electrode of the second transistor, and a voltage of the second electrode of the third transistor forms a scanning circuit output.