CMOS Device Fabrication Using Silicon Coating Barrier
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Solution Overview
Problem
The fabrication of CMOS devices faces challenges due to leakage current phenomena caused by nickel-silicide diffusion in NMOS and germanium atom segregation in PMOS, leading to increased resistance and signal delay.
Innovation Solution
A method involving the formation of isolating structures, epitaxial layers, and a metal silicide layer, with a silicon or silicon-germanium coating layer to prevent nickel-silicide diffusion and germanium segregation, enhancing the CMOS device's performance by reducing resistance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal silicide layer (e.g., nickel-silicide) is formed on the source/drain region to reduce resistance and improve ohmic contacts, then the performance of the CMOS is improved, but the nickel-silicide diffuses into the silicon substrate and channel, generating piping defects and leakage current
Solution Approach 1:
A silicon-containing coating layer is introduced as an intermediary barrier between the metal silicide layer and the silicon substrate. This coating layer prevents the diffusion of nickel-silicide into the channel while maintaining the low resistance properties of the metal silicide contact, thereby eliminating leakage current without sacrificing CMOS performance
Solution Approach 2:
The silicon-containing coating layer is formed on the source/drain region before the metal silicide layer is deposited. This preliminary action creates a diffusion barrier in advance, preventing the harmful diffusion of metal silicide into the silicon substrate during subsequent processing and device operation
2Productivity
If the size of semiconductor components is reduced to increase integrated density, then the integrated density of ICs is improved, but the fabrication process becomes more challenging and precise control is difficult
Solution Approach 1:
The invention changes the material parameter of the source/drain region by introducing a silicon-containing coating layer with specific crystalline structure and composition. This parameter change enables precise control of the diffusion barrier properties, allowing reliable fabrication even at reduced component sizes and enabling higher integrated density
3Reliability
If germanium atoms are segregated in the source/drain region of PMOS to increase carrier mobility, then the mobility of p-typed carrier is improved, but the germanium atoms aggregate, increasing resistance and generating leakage current
Solution Approach 1:
The silicon-containing coating layer is selectively formed only in the source/drain regions where germanium atoms are present. This local quality change prevents germanium aggregation in specific locations while maintaining high carrier mobility in the channel, thereby controlling resistance without sacrificing mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively avoids leakage current and resistance issues, improving the overall performance of the CMOS device by enhancing carrier mobility and reducing signal delay.
Implementation Method 1
a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first doped region and the second doped region
Implementation Method 2
a silicon-germanium (SiGe) epitaxial layer is filled in the openings to form a source/drain region
Data Source
AI summary
A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectively formed on the first and second gates. Next, an epitaxial layer is formed in the substrate on two sides of the second gate. Next, first and second spacers, first and second doped regions are formed. Next, a portion of the first spacer is removed to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer. Next, a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first and second doped regions. Next, the mask layer is removed. Next, a metal silicide layer is formed on the first and second gates and the silicon layer.