Low Resistance Source/Drain Contacts for CMOS Devices
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Solution Overview
Problem
Conventional metal liner contact schemes in nanometer scale CMOS devices face high contact resistivity issues, particularly in n-type and p-type field effect transistor regions, leading to performance limitations due to short channel concerns, dopant activation issues, and complexity in integrating trench epitaxy contacts.
Innovation Solution
The method involves implanting alloy elements in source/drain regions to form amorphized layers, which are then recrystallized using epitaxy processes to create metastable interfaces exceeding solubility limits, allowing for the formation of low resistance contacts in both n-type and p-type regions through solid or liquid phase epitaxy without additional gas phase epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal liner contact schemes are used in nanometer scale CMOS devices, then the manufacturing process is simple, but the contact resistivity is high (above 3×10−9 ohm·cm2, typically approximately 5×10−9 ohm·cm2)
Solution Approach 1:
The patent changes the physical and chemical parameters of the contact interface by forming metastable recrystallized interfaces with alloy element concentrations exceeding solubility limits. This parameter change achieves contact resistivity of approximately 2.5×10−9 ohm·cm2 or below, resolving the contradiction between simple manufacturing and low contact resistivity.
Solution Approach 2:
The patent uses composite material structures by implanting first and second alloy elements to form amorphized layers that are subsequently recrystallized. The resulting metastable recrystallized interfaces create a composite contact structure with superior electrical properties, achieving low contact resistivity while maintaining process integration.
2Quantity of substance
If source/drain implantation processes are used to increase dopant concentration, then the dopant concentration can be high exceeding chemical solubility limits, but excess implanted dopants are not activated and segregate into stable clusters or precipitates
Solution Approach 1:
The patent applies preliminary amorphization treatment before recrystallization. By implanting alloy elements to form amorphized layers first, and then recrystallizing them to form metastable interfaces, the process activates dopants effectively while maintaining high concentrations above solubility limits, preventing precipitation and clustering.
Solution Approach 2:
The patent utilizes phase transitions by transforming the amorphized layers into metastable recrystallized interfaces. This phase transition from amorphous to crystalline state activates the implanted dopants, enabling high dopant concentration with effective activation while avoiding the formation of stable clusters or precipitates.
3Reliability
If trench epitaxy contacts are integrated, then contact resistivity can be reduced, but the process becomes complicated and challenging due to separate growth of n-type and p-type epitaxy materials in Middle-Of-Line post source/drain and gate formation
Solution Approach 1:
The patent merges the contact formation process with the existing source/drain implantation and recrystallization steps. By implanting alloy elements during source/drain processing and recrystallizing them in-situ, the method combines multiple functions into a unified process, achieving low contact resistivity without the complexity of separate trench epitaxy growth for n-type and p-type materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves contact resistivities of approximately 2.5×10−9 ohm·cm2 or below for both NFET and PFET regions, enhancing CMOS device performance while maintaining compatibility and avoiding short channel impacts.
Implementation Method 1
First alloy elements are implanted in the S/D regions in the NFET region, and second alloy elements are implanted in the PFET region
Implementation Method 2
The first and second alloy elements form respective amorphized layers on the S/D regions
Implementation Method 3
The amorphized layers are recrystallized to form metastable recrystallized interfaces using an epitaxy process
Implementation Method 4
recrystallizing the amorphized layer in the NFET region at a first thermal budget to form metastable recrystallized interfaces using a solid phase epitaxy process
Implementation Method 5
recrystallizing the amorphized layer in the PFET region at a second thermal budget lower than the first thermal budget to form metastable recrystallized interfaces using a liquid phase epitaxy process
Implementation Method 6
recrystallizing the amorphized layer in the NFET region at a first thermal budget... recrystallizing the amorphized layer in the PFET region at a second thermal budget lower than the first thermal budget
Data Source
AI summary
A method for fabricating a semiconductor device includes accessing source/drain regions (S/D) in an n-type field effect transistor (NFET) region and in a p-type field effect transistor (PFET) region. First alloy elements are implanted in the S/D regions in the NFET region, and second alloy elements are implanted in the PFET region with the NFET region blocked. The first and second alloy elements form respective amorphized layers on the S/D regions in respective NFET and PFET regions. The amorphized layers are recrystallized to form metastable recrystallized interfaces using an epitaxy process wherein the metastable recrystallized interfaces formed in respective NFET and PFET regions exceed solubility of the first and second alloy elements in respective materials of the S/D regions in the NFET and PFET regions. Contacts to the metastable recrystallized layers of the S/D regions in the NFET and PFET regions are concurrently formed.