CMOS Gate Spacer Removal During Silicidation to Prevent Voids
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Solution Overview
Problem
In the manufacturing of CMOS transistors, the formation of residual voids between adjacent gates due to the difficulty in filling gaps with a dielectric material leads to short-circuits, and current methods to address this, such as etching spacers, damage the semiconductor material and require additional cleaning steps.
Innovation Solution
A method where the second spacers are removed during the silicidation process before the silicided portions are fully formed, eliminating the need for subsequent cleaning and reducing the risk of metal residue deposition, thereby preventing short-circuits and preserving the semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between two adjacent gates is reduced to increase transistor density, then the overall performance of CMOS circuit is improved, but the gaps between gates become difficult to fill completely leading to formation of residual voids
Solution Approach 1:
The method performs preliminary actions by forming stress liners and performing first spacer removal before gate alignment, while delaying second spacer removal until after gate alignment. This sequencing prevents void formation by ensuring proper gap geometry is established before critical filling operations, resolving the contradiction between high density and complete gap filling.
2Manufacturing precision
If etching of spacers is performed to increase gap width and prevent void formation, then the gap filling is improved, but the semiconductor material, silicided portions, and STIs are damaged
Solution Approach 1:
The invention applies local quality by differentiating the treatment of first and second spacers. First spacers are removed selectively to create gaps, while second spacers are removed only after gate alignment to protect critical areas. This localized approach ensures gap filling quality without causing widespread damage to semiconductor material, silicided portions, or STIs.
3Reliability
If a cleaning step is added to remove metal residues, then the short-circuit risk is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The method converts the potentially harmful effect of metal residue deposition into a beneficial outcome by timing the second spacer removal to occur after gate alignment. Any metal residues deposited during this controlled timing are positioned safely away from critical gate areas, eliminating the need for additional cleaning steps while maintaining short-circuit prevention.
4Productivity
If the thickness of the stress liner is increased to improve transistor performance, then the individual transistor performance is improved, but the height/width form factor of gaps increases making them difficult to fill
Solution Approach 1:
The invention performs preliminary removal of first spacers and formation of stress liners before gate alignment, establishing optimal gap geometry in advance. This preliminary action compensates for the increased height/width form factor caused by thicker stress liners, ensuring complete gap filling is achieved before the gaps become difficult to fill.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively limits the formation of residual voids and eliminates the need for a metal residue cleaning step, improving the reliability of CMOS circuits by maintaining the integrity of the semiconductor material and reducing the complexity of the manufacturing process.
Implementation Method 1
siliciding the gates so as to form the silicided portions of the gates
Implementation Method 2
silicidation of the gates comprising the following sub-steps of: i. Depositing a nickel-platinum NiPt alloy at the tops of the gates, ii. Carrying out a first thermal anneal so as to diffuse and react part of the Nickel Ni in said NiPt alloy at the upper portions of the gates
Data Source
AI summary
A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.