CMOS Spike Generation Circuit With Narrow Pulses and Lower Power
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Solution Overview
Problem
Spike generator circuits, such as those used in neural networks, face challenges in reducing power consumption while maintaining efficient spike signal generation.
Innovation Solution
The proposed spike generation circuit incorporates a CMOS inverter, a switch, an inverting circuit, and a delay circuit, with specific configurations of CMOS inverters and capacitance elements to control signal inversion and delay, resulting in a spike signal with a narrow pulse width and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a spike generator circuit is designed to generate spike signals with steep rise and fall times, then the signal quality and neural network performance are improved, but the power consumption increases due to higher current flow during signal transitions
Solution Approach 1:
The circuit uses periodic switching action through the switch element connected to the capacitor, where the capacitor is charged and discharged in periodic cycles to generate spike signals. This periodic charging/discharging mechanism enables steep rise and fall times while controlling power consumption by limiting current flow to discrete transition periods rather than continuous operation
Solution Approach 2:
The circuit changes the operational parameters of the CMOS inverter by controlling the voltage across the capacitor. The inverter operates in different regions (linear vs. saturation) depending on the capacitor voltage, enabling the generation of steep spike transitions. The parameter change from steady-state to transient operation allows high-speed signal generation with controlled energy dissipation
2Loss of time
If the pulse width of the spike signal is reduced to improve temporal precision, then the timing resolution in neural networks is enhanced, but the power consumption increases due to more frequent switching operations
Solution Approach 1:
The circuit generates narrow pulse widths through periodic charging and discharging of the capacitor, where each charge-discharge cycle produces a discrete spike event. The periodic nature of this operation allows precise temporal control with narrow pulse widths while managing power consumption by confining current flow to brief transition intervals rather than continuous operation
Solution Approach 2:
The capacitor in the circuit serves a dual function: it stores energy during the charging phase and automatically discharges to generate the spike signal, eliminating the need for separate discharge control circuitry. This self-service mechanism reduces overall circuit complexity and power consumption while maintaining precise pulse width control
Data Source
AI summary
A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.