CMOS Storage Element SEU Mitigation via N-Well Extraction
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Solution Overview
Problem
As feature sizes of semiconductor devices decrease, the occurrence of single event upsets (SEUs) increases, and conventional techniques for mitigating SEUs often require significant area and impose performance penalties.
Innovation Solution
Implementing a CMOS storage element within a p-type substrate with an independent n-well that is separated by a minimum distance, using design rules to optimize the size and placement of n-wells around storage elements, and incorporating mitigating circuit elements to reduce susceptibility to SEUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SEU mitigation techniques (redundancy, triplication, error code correction) are used, then SEU resistance is improved, but area and performance are penalized
Solution Approach 1:
The patent extracts the problematic n-well structures from proximity to storage elements and relocates them to distant regions of the substrate. This separation removes the source of SEU susceptibility while avoiding the area overhead of redundancy techniques. The n-wells are taken out from their harmful proximity to storage elements and placed in isolated regions, achieving SEU mitigation without replicating storage structures.
Solution Approach 2:
The patent segments the substrate into distinct regions: storage element regions and isolated n-well regions separated by minimum distances. This spatial segmentation creates physical isolation between sensitive storage elements and potentially harmful n-well structures, reducing SEU coupling while maintaining compact layout without requiring redundant storage structures.
2Reliability
If conventional SEU mitigation techniques (redundancy, triplication, error code correction) are used, then SEU resistance is improved, but performance is penalized
Solution Approach 1:
By extracting n-wells from proximity to storage elements and relocating them to distant isolated regions, the patent eliminates the performance degradation caused by SEU mitigation overhead. The storage elements operate independently without the performance penalty of redundant structures or complex error correction logic, achieving both high reliability and maintained performance.
3Area of moving object
If feature sizes of devices are decreased, then device density is improved, but SEU occurrence rate increases
Solution Approach 1:
The patent addresses the SEU density trade-off by transitioning from planar proximity-based design to spatial separation-based design. Instead of relying on larger spacing that reduces density, the patent uses dimensional separation by placing n-wells in isolated regions distant from storage elements, achieving both high device density and low SEU occurrence through strategic spatial arrangement in the substrate plane.
Solution Approach 2:
The substrate is segmented into functional zones with minimum distance separation between storage elements and n-wells. This segmentation allows compact high-density integration of storage elements while isolating them from SEU-generating n-well regions, achieving both high density and high reliability through spatial zoning.
Data Source
AI summary
A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.