CMOS Image Sensor Superlattice Transistor Mobility
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Solution Overview
Problem
Current semiconductor devices, such as CMOS image sensors, face limitations in achieving enhanced charge carrier mobility and reduced noise, particularly in the context of advanced materials and processing techniques.
Innovation Solution
The implementation of a superlattice structure in CMOS image sensors, comprising stacked semiconductor monolayers with non-semiconductor monolayers constrained within the crystal lattice, which reduces the effective mass of charge carriers and enhances mobility, while also acting as a barrier to dopant diffusion and scattering, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then device simplicity is maintained, but charge carrier mobility is limited
Solution Approach 1:
The patent employs a composite superlattice structure comprising alternating layers of silicon and silicon-germanium materials. This composite architecture enables enhanced charge carrier mobility through strain engineering while maintaining compatibility with conventional CMOS fabrication processes, thus improving speed without proportionally increasing device complexity
Solution Approach 2:
The invention modifies the crystal lattice parameters by introducing controlled strain through the silicon-germanium layers. This parameter change alters the band structure and effective mass of charge carriers, resulting in enhanced mobility while keeping the overall device structure relatively simple
2Reliability
If dopant diffusion is increased to improve conductivity, then electrical conductivity is enhanced, but device precision deteriorates
Solution Approach 1:
The patent extracts the dopant diffusion function from the conventional bulk silicon structure and relocates it to the superlattice interface regions. This extraction allows for controlled dopant segregation at the silicon-silicon-germanium interfaces, enhancing conductivity through localized doping while maintaining precise spatial control over dopant distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in increased charge carrier mobility, reduced gate leakage, and decreased fixed pattern noise, enabling improved performance and efficiency in CMOS image sensors.
Implementation Method 1
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 2
acting as a barrier to dopant diffusion and scattering
Data Source
AI summary
A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.