CMOS Switch Circuit With Body Biasing for Low Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistor-based switch implementations face challenges in achieving low, signal-independent on-resistance when turned on and low leakage current when turned off, especially with the scaling of device sizes and reduced power supply and threshold voltages in fabrication processes.
Innovation Solution
The use of a switch circuit with NMOS and PMOS pass-through transistors and a switch network that connects the sources and bodies of the transistors in specific configurations to reduce on-resistance and increase threshold voltages, thereby minimizing leakage current, by employing active and inactive states of switching signals to control the connection of reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are scaled downward to provide higher frequency operation and reduced power consumption, then productivity and energy efficiency are improved, but on-resistance increases and leakage current worsens due to reduced power supply and threshold voltages
Solution Approach 1:
The patent combines NMOS and PMOS transistors in a complementary configuration where the PMOS transistor compensates for the increased on-resistance of the scaled NMOS transistor. This merging of opposite-type transistors creates a push-pull structure that maintains low overall on-resistance while benefiting from the smaller device size and lower power consumption.
Solution Approach 2:
The patent changes the voltage parameters by introducing a boosted voltage (VBST) that is higher than the standard power supply voltage. This parameter change allows the transistors to operate with enhanced gate-drive voltages, compensating for the reduced threshold voltages caused by device scaling and maintaining strong switching performance despite smaller dimensions.
2Use of energy by moving object
If device sizes are scaled downward to reduce power consumption, then energy usage is improved, but leakage current increases due to reduced threshold voltages
Solution Approach 1:
The patent applies preliminary anti-action by using the PMOS transistor to counteract the leakage current generated by the NMOS transistor before it can affect the circuit operation. The complementary transistor is positioned and biased to actively oppose the harmful leakage effect, neutralizing it in advance.
Solution Approach 2:
The patent changes the voltage parameters by introducing a boosted voltage (VBST) that is higher than the standard power supply voltage. This parameter change allows the transistors to operate with enhanced gate-drive voltages, compensating for the reduced threshold voltages caused by device scaling and maintaining strong switching performance despite smaller dimensions.
3Device complexity
If a single transistor is used to implement a switch, then device complexity is reduced, but on-resistance becomes signal-dependent and cannot be kept low
Solution Approach 1:
The patent combines NMOS and PMOS transistors in a complementary configuration where the PMOS transistor compensates for the increased on-resistance of the scaled NMOS transistor. This merging of opposite-type transistors creates a push-pull structure that maintains low overall on-resistance while benefiting from the smaller device size and lower power consumption.
Data Source
AI summary
A switch can be implemented by a switch circuit, which can include a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal, and a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal. The switch circuit can also include a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage. A capacitance-to-voltage converter can include one or more of the switch circuits.