CMOS Analog Switch Buffer Transistors for Low GIDL Leakage
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) current in CMOS switches significantly impacts the performance of analog circuits, especially when multiple switches are in the off-state, as it leads to combined leakage currents that can hinder system performance.
Innovation Solution
An analog switch design featuring NMOS and PMOS circuits in parallel, with buffer transistors and a control circuit that applies modulated gate voltages between supply voltage and GIDL mitigation voltage based on the switch state to reduce GIDL current, ensuring the buffer transistors are either off or in a high resistance state when the switch is off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple CMOS switches are used in parallel with standard gate control, then the switch can handle higher current and provide better signal transmission, but the combined GIDL current from multiple off-state switches significantly increases leakage and degrades system performance
Solution Approach 1:
The patent divides each CMOS switch into two separate transistors: a switch transistor for signal transmission and a buffer transistor for leakage control. This segmentation allows independent optimization of signal handling and leakage reduction functions, enabling multiple switches to be used in parallel without cumulative GIDL problems affecting overall system performance
Solution Approach 2:
The buffer transistor acts as an intermediary between the switch transistor and the off-state leakage path. By positioning the buffer transistor in series with the switch transistor and controlling its gate voltage independently, the patent creates a control mechanism that blocks GIDL current while maintaining signal transmission capability when the switch is on
2Loss of energy
If buffer transistors are added to reduce GIDL current, then leakage is minimized, but the device complexity and number of components increase
Solution Approach 1:
The buffer transistor serves multiple functions: it blocks GIDL current when the switch is off, maintains low leakage across varying gate and drain voltages, and can be controlled by a simple modulated gate voltage signal. This multi-functionality justifies the additional component by providing comprehensive leakage control without requiring multiple separate control circuits
Solution Approach 2:
The patent changes the gate voltage parameter of the buffer transistor dynamically - applying a modulated gate voltage that switches between different levels based on the switch state. When the main switch is off, the buffer transistor gate voltage is adjusted to maximize leakage blocking; when the main switch is on, the buffer transistor gate voltage is adjusted to maintain low leakage while allowing signal transmission
3Loss of energy
If the switch is kept in the off-state to reduce leakage, then power consumption is minimized, but the switch cannot perform signal transmission when needed
Solution Approach 1:
The patent implements dynamic control of the buffer transistor gate voltage that adapts to the switch state. The modulated gate voltage signal dynamically adjusts the buffer transistor's conductivity - keeping it in a high-resistance state during off-periods to minimize leakage, and transitioning it to a low-resistance state during on-periods to enable signal transmission without significant leakage penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces GIDL current, minimizing leakage and enhancing the performance of analog switches in applications like multiplexers and de-multiplexers by maintaining low leakage currents across a range of gate and drain voltages, thereby improving overall circuit efficiency.
Implementation Method 1
The main sources of leakage in the off-state are the sub-threshold leakage current and the gate-induced drain leakage (GIDL) current. GIDL current is caused by high field effect in the drain junction of metal oxide semiconductor (MOS) transistors.
Data Source
AI summary
In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.